ad9680_debug.c 38.4 KB
Newer Older
Rene Habraken's avatar
Rene Habraken committed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
/*
 * Driver for AD9680 and similar high-speed Analog-to-Digital converters
 *
 * Copyright 2012-2017 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#define DEBUG

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>

#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>

#include "cf_axi_adc.h"

#define AD9680_REG_CHIP_ID_LOW		0x004
#define AD9680_REG_CHIP_ID_HIGH		0x005
#define AD9680_REG_DEVICE_INDEX		0x008
#define AD9680_REG_PAIR_INDEX		0x009
#define AD9680_REG_INPUT_FS_RANGE	0x025
#define AD9680_REG_CHIP_PIN_CTRL	0x040

#define AD9680_REG_OUTPUT_MODE		0x561
#define AD9680_REG_TEST_MODE		0x550

#define AD9680_REG_THRESH_CTRL		0x245
#define AD9680_REG_THRESH_HI_LSB	0x247
#define AD9680_REG_THRESH_HI_MSB	0x248
#define AD9680_REG_THRESH_LOW_LSB	0x249
#define AD9680_REG_THRESH_LOW_MSB	0x24A

#define AD9680_REG_CHIP_PIN_CTRL_MASK(chn)	(0x07 << (3 * (chn)))

#define AD9680_TESTMODE_OFF			0x0
#define AD9680_TESTMODE_MIDSCALE_SHORT		0x1
#define AD9680_TESTMODE_POS_FULLSCALE		0x2
#define AD9680_TESTMODE_NEG_FULLSCALE		0x3
#define AD9680_TESTMODE_ALT_CHECKERBOARD	0x4
#define AD9680_TESTMODE_PN23_SEQ		0x5
#define AD9680_TESTMODE_PN9_SEQ			0x6
#define AD9680_TESTMODE_ONE_ZERO_TOGGLE		0x7
#define AD9680_TESTMODE_USER			0x8
#define AD9680_TESTMODE_RAMP			0xF

#define AD9680_OUTPUT_MODE_OFFSET_BINARY	0x0
#define AD9680_OUTPUT_MODE_TWOS_COMPLEMENT	0x1

#define CHIPID_AD9680			0xC5
#define CHIPID_AD9684			0xD2
#define CHIPID_AD9234			0xCE
#define CHIPID_AD9694			0xDB
#define CHIPID_AD9094			0xE8

enum {
	ID_AD9234,
	ID_AD9680,
	ID_AD9680_x2,
	ID_AD9684,
	ID_AD9694,
	ID_AD9094,
};

enum ad9680_sysref_mode {
	AD9680_SYSREF_DISABLED,
	AD9680_SYSREF_CONTINUOUS,
	AD9680_SYSREF_ONESHOT
};

struct ad9680_sysref_config {
	enum ad9680_sysref_mode mode;
	bool capture_falling_edge;
	bool valid_falling_edge;
};

struct ad9680_jesd204_link_config {
	uint8_t did;
	uint8_t bid;

	uint8_t num_lanes;
	uint8_t num_converters;
	uint8_t octets_per_frame;
	uint8_t frames_per_multiframe;

	uint8_t bits_per_sample;
	uint8_t converter_resolution;

	uint8_t lid[4];
	uint8_t lane_mux[4];

	bool scrambling;
	uint8_t subclass;

	struct ad9680_sysref_config sysref;
};

static int ad9680_spi_read(struct spi_device *spi, unsigned int reg)
{
	unsigned char buf[3];
	int ret;

	if (spi) {
		buf[0] = 0x80 | (reg >> 8);
		buf[1] = reg & 0xFF;

		ret = spi_write_then_read(spi, &buf[0], 2, &buf[2], 1);

		dev_dbg(&spi->dev, "%s: REG: 0x%X VAL: 0x%X (%d)\n",
			__func__, reg, buf[2], ret);

		if (ret < 0)
			return ret;

		return buf[2];
	}
	return -ENODEV;
}

static int ad9680_spi_write(struct spi_device *spi, unsigned int reg,
	unsigned int val)
{
	unsigned char buf[3];
	int ret;

	if (spi) {
		buf[0] = reg >> 8;
		buf[1] = reg & 0xFF;
		buf[2] = val;
		ret = spi_write_then_read(spi, buf, 3, NULL, 0);
		if (ret < 0)
			return ret;

		dev_dbg(&spi->dev, "%s: REG: 0x%X VAL: 0x%X (%d)\n",
			__func__, reg, val, ret);

		return 0;
	}

	return -ENODEV;
}

static int ad9680_reg_access(struct iio_dev *indio_dev, unsigned int reg,
	unsigned int writeval, unsigned int *readval)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
	struct spi_device *spi = conv->spi;
	int ret;

	if (readval == NULL)
		return ad9680_spi_write(spi, reg, writeval);

	ret = ad9680_spi_read(spi, reg);
	if (ret < 0)
		return ret;
	*readval = ret;

	return 0;
}

static int ad9680_select_channel(struct axiadc_converter *conv,
	int chan)
{
	unsigned int device, pair;
	int ret;

	if (chan >= 0) {
		device = BIT(chan & 0x1);
		pair = BIT((chan >> 1) & 1);
	} else {
		device = 0x3;
		pair = 0x3;
	}

	ret = ad9680_spi_write(conv->spi, AD9680_REG_DEVICE_INDEX, device);
	if (ret < 0)
		return ret;
	return ad9680_spi_write(conv->spi, AD9680_REG_PAIR_INDEX, pair);
}

static int ad9680_channel_write(struct axiadc_converter *conv,
	unsigned int chan, unsigned int reg, unsigned int val)
{
	int ret;

	ret = ad9680_select_channel(conv, chan);
	ret |= ad9680_spi_write(conv->spi, reg, val);
	ret |= ad9680_select_channel(conv, -1);

	return ret;
}

static int ad9680_channel_read(struct axiadc_converter *conv,
	unsigned int chan, unsigned int reg)
{
	int ret;

	ad9680_select_channel(conv, chan);
	ret = ad9680_spi_read(conv->spi, reg);
	ad9680_select_channel(conv, -1);

	return ret;
}

static unsigned int ad9680_pnsel_to_testmode(enum adc_pn_sel sel)
{
	switch (sel) {
	case ADC_PN9:
		return AD9680_TESTMODE_PN9_SEQ;
	case ADC_PN23A:
		return AD9680_TESTMODE_PN23_SEQ;
	default:
		return AD9680_TESTMODE_OFF;
	}
}

static int ad9680_outputmode_set(struct spi_device *spi, unsigned int mode)
{
	int ret;

	ret = ad9680_spi_write(spi, AD9680_REG_OUTPUT_MODE, mode);
	if (ret < 0)
		return ret;

	return ad9680_spi_write(spi, AD9680_REG_TEST_MODE,
				AD9680_TESTMODE_OFF);
}

static int ad9680_testmode_set(struct iio_dev *indio_dev, unsigned int chan,
	unsigned int mode)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);

	ad9680_channel_write(conv, chan, AD9680_REG_TEST_MODE, mode);
	conv->testmode[chan] = mode;

	return 0;
}

static int ad9680_set_pnsel(struct iio_dev *indio_dev, unsigned int chan,
	enum adc_pn_sel sel)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
	unsigned int mode = ad9680_pnsel_to_testmode(sel);
	unsigned int output_mode;
	int ret;

	output_mode = conv->adc_output_mode;
	if (mode != AD9680_TESTMODE_OFF)
		output_mode &= ~AD9680_OUTPUT_MODE_TWOS_COMPLEMENT;

	ret = ad9680_spi_write(conv->spi, AD9680_REG_OUTPUT_MODE, output_mode);
	if (ret < 0)
		return ret;

	return ad9680_testmode_set(indio_dev, chan, mode);
}

static irqreturn_t ad9680_event_handler(struct axiadc_converter *conv,
	unsigned int chn)
{
	u64 event = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, chn,
			IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING);
	s64 timestamp = iio_get_time_ns(conv->indio_dev);

	if (conv->indio_dev)
		iio_push_event(conv->indio_dev, event, timestamp);

	return IRQ_HANDLED;
}

static irqreturn_t ad9680_fdA_handler(int irq, void *private)
{
	return ad9680_event_handler(private, 0);
}

static irqreturn_t ad9680_fdB_handler(int irq, void *private)
{
	return ad9680_event_handler(private, 1);
}

static int ad9680_read_thresh(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, enum iio_event_type type,
	enum iio_event_direction dir, enum iio_event_info info, int *val,
	int *val2)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
	struct spi_device *spi = conv->spi;
	u16 low, high;

	mutex_lock(&indio_dev->mlock);
	low = (ad9680_spi_read(spi, AD9680_REG_THRESH_LOW_MSB) << 8) |
		ad9680_spi_read(spi, AD9680_REG_THRESH_LOW_LSB);
	high = (ad9680_spi_read(spi, AD9680_REG_THRESH_HI_MSB) << 8) |
		ad9680_spi_read(spi, AD9680_REG_THRESH_HI_LSB);
	mutex_unlock(&indio_dev->mlock);

	switch (info) {
	case IIO_EV_INFO_HYSTERESIS:
		*val = high - low;
		break;
	case IIO_EV_INFO_VALUE:
		*val = high;
		break;
	default:
		return -EINVAL;
	}

	return IIO_VAL_INT;
}

static int ad9680_read_thresh_en(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, enum iio_event_type type,
	enum iio_event_direction dir)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
	struct spi_device *spi = conv->spi;
	int ret;

	ret = ad9680_spi_read(spi, AD9680_REG_CHIP_PIN_CTRL);
	if (ret < 0)
		return ret;
	else
		return !(ret & AD9680_REG_CHIP_PIN_CTRL_MASK(chan->channel));
}

static int ad9680_write_thresh(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, enum iio_event_type type,
	enum iio_event_direction dir, enum iio_event_info info, int val,
	int val2)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
	struct spi_device *spi = conv->spi;
	int ret = 0;
	int low, high;

	mutex_lock(&indio_dev->mlock);
	high = (ad9680_spi_read(spi, AD9680_REG_THRESH_HI_MSB) << 8) |
		ad9680_spi_read(spi, AD9680_REG_THRESH_HI_LSB);

	switch (info) {
	case IIO_EV_INFO_HYSTERESIS:
		if (val < 0) {
			ret = -EINVAL;
			goto unlock;
		}

		low = high - val;
		break;

	case IIO_EV_INFO_VALUE:
		if (val > 0x7FF) {
			ret = -EINVAL;
			goto unlock;
		}

		ad9680_spi_write(spi, AD9680_REG_THRESH_HI_MSB, val >> 8);
		ad9680_spi_write(spi, AD9680_REG_THRESH_HI_LSB, val & 0xFF);

		/* Calculate the new lower threshold limit */
		low = (ad9680_spi_read(spi, AD9680_REG_THRESH_LOW_MSB) << 8) |
			ad9680_spi_read(spi, AD9680_REG_THRESH_LOW_LSB);
		low = val - high + low;
		break;

	default:
		ret = -EINVAL;
		goto unlock;
	}

	if (low < 0)
		low = 0;
	ad9680_spi_write(spi, AD9680_REG_THRESH_LOW_MSB, low >> 8);
	ad9680_spi_write(spi, AD9680_REG_THRESH_LOW_LSB, low & 0xFF);

unlock:
	mutex_unlock(&indio_dev->mlock);
	return ret;
}

static int ad9680_write_thresh_en(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, enum iio_event_type type,
	enum iio_event_direction dir, int state)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
	struct spi_device *spi = conv->spi;
	int ret;

	mutex_lock(&indio_dev->mlock);

	ret = ad9680_spi_read(spi, AD9680_REG_CHIP_PIN_CTRL);
	if (ret < 0)
		goto err_unlock;

	if (state)
		ret &= ~AD9680_REG_CHIP_PIN_CTRL_MASK(chan->channel);
	else
		ret |= AD9680_REG_CHIP_PIN_CTRL_MASK(chan->channel);

	ret = ad9680_spi_write(spi, AD9680_REG_CHIP_PIN_CTRL, ret);
err_unlock:
	mutex_unlock(&indio_dev->mlock);
	return ret;
}

static const int ad9680_scale_table[][2] = {
	{1460, 0x08}, {1580, 0x09}, {1700, 0x0A}, {1820, 0x0B},
	{1940, 0x00}, {2060, 0x0C},
};

static const int ad9694_scale_table[][2] = {
	{1440, 0xa}, {1560, 0xb}, {1680, 0xc}, {1800, 0xd},
	{1920, 0xe}, {2040, 0xf}, {2160, 0x0},
};

static void ad9680_scale(struct axiadc_converter *conv, int index,
	unsigned int *val, unsigned int *val2)
{
	unsigned int tmp;

	if (index > conv->chip_info->num_scales) {
		*val = 0;
		*val2 = 0;
		return;
	}

	tmp = (conv->chip_info->scale_table[index][0] * 1000000ULL) >>
		    conv->chip_info->channel[0].scan_type.realbits;
	*val = tmp / 1000000;
	*val2 = tmp % 1000000;
}

static ssize_t ad9680_show_scale_available(struct iio_dev *indio_dev,
	uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
	unsigned int scale[2];
	int i, len = 0;

	for (i = 0; i < conv->chip_info->num_scales; i++) {
		ad9680_scale(conv, i, &scale[0], &scale[1]);
		len += sprintf(buf + len, "%u.%06u ", scale[0], scale[1]);
	}

	/* replace last space with a newline */
	buf[len - 1] = '\n';

	return len;
}

static int ad9680_get_scale(struct axiadc_converter *conv,
	const struct iio_chan_spec *chan, int *val, int *val2)
{
	unsigned int vref_val;
	unsigned int i;

	switch (conv->id) {
	case CHIPID_AD9694:
	case CHIPID_AD9094:
		vref_val = ad9680_channel_read(conv, chan->channel, 0x1910);
		break;
	default:
		vref_val = ad9680_spi_read(conv->spi, AD9680_REG_INPUT_FS_RANGE);
		break;
	}
	vref_val &= 0xf;

	for (i = 0; i < conv->chip_info->num_scales; i++) {
		if (vref_val == conv->chip_info->scale_table[i][1])
			break;
	}

	ad9680_scale(conv, i, val, val2);

	return IIO_VAL_INT_PLUS_MICRO;
}

static int ad9680_set_scale(struct axiadc_converter *conv,
	const struct iio_chan_spec *chan, int val, int val2)
{
	unsigned int scale_val[2];
	unsigned int scale_raw;
	unsigned int i;

	for (i = 0; i < conv->chip_info->num_scales; i++) {
		ad9680_scale(conv, i, &scale_val[0], &scale_val[1]);
		if (scale_val[0] != val || scale_val[1] != val2)
			continue;

		scale_raw = conv->chip_info->scale_table[i][1];

		switch (conv->id) {
		case CHIPID_AD9694:
		case CHIPID_AD9094:
			ad9680_channel_write(conv, chan->channel, 0x1910,
					     scale_raw);
			break;
		default:
			ad9680_spi_write(conv->spi, AD9680_REG_INPUT_FS_RANGE,
					 scale_raw);
			break;
		}
		return 0;
	}

	return -EINVAL;
}

static int ad9680_testmode_read(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan)
{
	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);

	return conv->testmode[chan->channel];
}

static int ad9680_testmode_write(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, unsigned int item)
{
	int ret;

	mutex_lock(&indio_dev->mlock);
	ret = ad9680_testmode_set(indio_dev, chan->channel, item);
	mutex_unlock(&indio_dev->mlock);

	return ret;
}

static const char * const ad9680_testmodes[] = {
	[AD9680_TESTMODE_OFF] = "off",
	[AD9680_TESTMODE_MIDSCALE_SHORT] = "midscale_short",
	[AD9680_TESTMODE_POS_FULLSCALE] = "pos_fullscale",
	[AD9680_TESTMODE_NEG_FULLSCALE] = "neg_fullscale",
	[AD9680_TESTMODE_ALT_CHECKERBOARD] = "checkerboard",
	[AD9680_TESTMODE_PN23_SEQ] = "pn_long",
	[AD9680_TESTMODE_PN9_SEQ] = "pn_short",
	[AD9680_TESTMODE_ONE_ZERO_TOGGLE] = "one_zero_toggle",
	[AD9680_TESTMODE_USER] = "user",
	[AD9680_TESTMODE_RAMP] = "ramp",
};

static const struct iio_enum ad9680_testmode_enum = {
	.items = ad9680_testmodes,
	.num_items = ARRAY_SIZE(ad9680_testmodes),
	.set = ad9680_testmode_write,
	.get = ad9680_testmode_read,
};

static struct iio_chan_spec_ext_info axiadc_ext_info[] = {
	IIO_ENUM("test_mode", IIO_SEPARATE, &ad9680_testmode_enum),
	IIO_ENUM_AVAILABLE("test_mode", &ad9680_testmode_enum),
	{
		.name = "scale_available",
		.read = ad9680_show_scale_available,
		.shared = true,
	},
	{},
};

static const struct iio_event_spec ad9680_events[] = {
	{
		.type = IIO_EV_TYPE_THRESH,
		.dir = IIO_EV_DIR_RISING,
		.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
				       BIT(IIO_EV_INFO_HYSTERESIS),
		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
	},
};

#define AD9680_CHAN(_chan, _si, _bits, _sign, _shift, _ev, _nb_ev)	\
	{ .type = IIO_VOLTAGE,						\
	  .indexed = 1,							\
	  .channel = _chan,						\
	  .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |	\
			BIT(IIO_CHAN_INFO_SAMP_FREQ),			\
	  .ext_info = axiadc_ext_info,			\
	  .scan_index = _si,						\
	  .scan_type = {						\
			.sign = _sign,					\
			.realbits = _bits,				\
			.storagebits = 16,				\
			.shift = _shift,				\
	  },								\
	  .event_spec = _ev,						\
	  .num_event_specs = _nb_ev,					\
	}

#define AD9694_CHAN(_chan) {						\
	.type = IIO_VOLTAGE,						\
	.indexed = 1,							\
	.channel = _chan,						\
	.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE),			\
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.ext_info = axiadc_ext_info,					\
	.scan_index = _chan,						\
	.scan_type = {							\
		.sign = 'S',						\
609
		.realbits = 16,						\
Rene Habraken's avatar
Rene Habraken committed
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
		.storagebits = 16,					\
		.shift = 0,						\
	},								\
	.event_spec = ad9680_events,					\
	.num_event_specs = ARRAY_SIZE(ad9680_events),			\
}

static const struct axiadc_chip_info axiadc_chip_info_tbl[] = {
	[ID_AD9234] = {
		.name = "AD9234",
		.max_rate = 1000000000UL,
		.scale_table = ad9680_scale_table,
		.num_scales = ARRAY_SIZE(ad9680_scale_table),
		.num_channels = 2,
		.channel[0] = AD9680_CHAN(0, 0, 12, 'S', 0, NULL, 0),
		.channel[1] = AD9680_CHAN(1, 1, 12, 'S', 0, NULL, 0),
	},
	[ID_AD9680] = {
		.name = "AD9680",
		.max_rate = 1250000000UL,
		.scale_table = ad9680_scale_table,
		.num_scales = ARRAY_SIZE(ad9680_scale_table),
		.num_channels = 2,
		.channel[0] = AD9680_CHAN(0, 0, 14, 'S', 0,
			ad9680_events, ARRAY_SIZE(ad9680_events)),
		.channel[1] = AD9680_CHAN(1, 1, 14, 'S', 0,
			ad9680_events, ARRAY_SIZE(ad9680_events)),
	},
	[ID_AD9680_x2] = {
		.name = "AD9680",
		.max_rate = 1250000000UL,
		.scale_table = ad9680_scale_table,
		.num_scales = ARRAY_SIZE(ad9680_scale_table),
		.num_channels = 4,
		.num_shadow_slave_channels = 2,
		.channel[0] = AD9680_CHAN(0, 0, 14, 'S', 0,
			ad9680_events, ARRAY_SIZE(ad9680_events)),
		.channel[1] = AD9680_CHAN(1, 1, 14, 'S', 0,
			ad9680_events, ARRAY_SIZE(ad9680_events)),
		.channel[2] = AD9680_CHAN(2, 2, 14, 'S', 0,
			ad9680_events, ARRAY_SIZE(ad9680_events)),
		.channel[3] = AD9680_CHAN(3, 3, 14, 'S', 0,
			ad9680_events, ARRAY_SIZE(ad9680_events)),
	},
	[ID_AD9684] = {
		.name = "AD9684",
		.max_rate = 1250000000UL,
		.scale_table = ad9680_scale_table,
		.num_scales = ARRAY_SIZE(ad9680_scale_table),
		.num_channels = 2,
		.channel[0] = AD9680_CHAN(0, 0, 14, 'S', 0, NULL, 0),
		.channel[1] = AD9680_CHAN(1, 1, 14, 'S', 0, NULL, 0),
	},
	[ID_AD9694] = {
		.name = "AD9694",
		.max_rate = 1000000000UL,
		.scale_table = ad9694_scale_table,
		.num_scales = ARRAY_SIZE(ad9694_scale_table),
		.num_channels = 4,
		.channel[0] = AD9694_CHAN(0),
		.channel[1] = AD9694_CHAN(1),
		.channel[2] = AD9694_CHAN(2),
		.channel[3] = AD9694_CHAN(3),
	},
	[ID_AD9094] = {
		.name = "AD9094",
		.max_rate = 1000000000UL,
		.scale_table = ad9694_scale_table,
		.num_scales = ARRAY_SIZE(ad9694_scale_table),
		.num_channels = 4,
		.channel[0] = AD9694_CHAN(0),
		.channel[1] = AD9694_CHAN(1),
		.channel[2] = AD9694_CHAN(2),
		.channel[3] = AD9694_CHAN(3),
	},
};

static bool ad9680_check_sysref_rate(unsigned int lmfc, unsigned int sysref)
{
	unsigned int div, mod;

	div = lmfc / sysref;
	mod = lmfc % sysref;

	/* Ignore minor deviations that can be introduced by rounding. */
	return mod <= div || mod >= sysref - div;
}

static int ad9680_update_sysref(struct axiadc_converter *conv,
				unsigned int lmfc)
{
	unsigned int n;
	int rate;

	/* No clock, no problem */
	if (!conv->sysref_clk)
		return 0;

	rate = clk_get_rate(conv->sysref_clk);
	if (rate < 0)
		return rate;

	/* If the current rate is OK, keep it */
	if (ad9680_check_sysref_rate(lmfc, rate))
		return 0;

	/*
	 * Try to find a rate that integer divides the LMFC. Starting with a low
	 * rate is a good idea and then slowly go up in case the clock generator
	 * can't generate such slow rates.
	 */
	for (n = 64; n > 0; n--) {
		rate = clk_round_rate(conv->sysref_clk, lmfc / n);
		if (ad9680_check_sysref_rate(lmfc, rate))
			break;
	}

	if (n == 0) {
		dev_err(&conv->spi->dev,
			"Could not find suitable SYSREF rate for LMFC of %u\n",
			lmfc);
		return -EINVAL;
	}

	return clk_set_rate(conv->sysref_clk, rate);
}

static ssize_t ad9680_status_read(struct device *dev,
	struct device_attribute *attr, char *buf)
{
	struct axiadc_converter *conv = dev_get_drvdata(dev);
	const char *hold_setup_desc;
	unsigned int hold, setup;
	int val;
	int ret;

	switch (conv->id) {
	case CHIPID_AD9694:
	case CHIPID_AD9094:
		val = ad9680_spi_read(conv->spi, 0x11b);
		break;
	default:
		val = ad9680_spi_read(conv->spi, 0x11c);
		break;
	}

	ret = scnprintf(buf, PAGE_SIZE, "Input clock %sdetected\n",
		(val & 0x01) ? "" : "not ");

	if (conv->id == CHIPID_AD9684)
		return ret;

	val = ad9680_spi_read(conv->spi, 0x56f);
	ret += scnprintf(buf + ret, PAGE_SIZE - ret,
		"JESD204 PLL is %slocked\n",
		(val & 0x80) ? "" : "not ");

	val = ad9680_spi_read(conv->spi, 0x12a);
	ret += scnprintf(buf + ret, PAGE_SIZE - ret,
		"SYSREF counter: %d\n", val);

	val = ad9680_spi_read(conv->spi, 0x128);
	hold = (val >> 4) & 0xf;
	setup = val & 0xf;

	if (hold == 0x0 && setup <= 0x7)
		hold_setup_desc = "Possible setup error";
	else if (hold <= 0x8 && setup == 0x8)
		hold_setup_desc = "No setup or hold error (best hold margin)";
	else if (hold == 0x8 && setup >= 0x9)
		hold_setup_desc = "No setup or hold error (best setup and hold margin)";
	else if (hold == 0x8 && setup == 0x0)
		hold_setup_desc = "No setup or hold error (best setup margin)";
	else if (hold >= 0x9 && setup == 0x0)
		hold_setup_desc = "Possible hold error";
	else
		hold_setup_desc = "Possible setup or hold error";

	ret += scnprintf(buf + ret, PAGE_SIZE - ret,
		"SYSREF hold/setup status: %s (%x/%x)\n",
		hold_setup_desc, hold, setup);

	return ret;
}

static DEVICE_ATTR(status, 0444, ad9680_status_read, NULL);

static int ad9680_setup_jesd204_link(struct axiadc_converter *conv,
	unsigned int sample_rate)
{
	unsigned long lane_rate_kHz;
	unsigned long sysref_rate;
	int ret;

	sysref_rate = DIV_ROUND_CLOSEST(sample_rate, 32);
805
	lane_rate_kHz = DIV_ROUND_CLOSEST(sample_rate, 50);
Rene Habraken's avatar
Rene Habraken committed
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943

	if (lane_rate_kHz < 3125000 || lane_rate_kHz > 12500000) {
		dev_err(&conv->spi->dev, "Lane rate %lu Mbps out of bounds. Must be between 3125 and 12500 Mbps",
			lane_rate_kHz / 1000);
		return -EINVAL;
	}

	if (lane_rate_kHz < 6250000)
		ad9680_spi_write(conv->spi, 0x56e, 0x10);	// low line rate mode must be enabled
	else
		ad9680_spi_write(conv->spi, 0x56e, 0x00);	// low line rate mode must be disabled

	ret = ad9680_update_sysref(conv, sysref_rate);
	if (ret < 0) {
		dev_err(&conv->spi->dev, "Failed to set SYSREF clock to %lu kHz: %d\n",
			sysref_rate / 1000, ret);
		return ret;
	}

	ret = clk_set_rate(conv->lane_clk, lane_rate_kHz);
	if (ret < 0) {
		dev_err(&conv->spi->dev, "Failed to set lane rate to %lu kHz: %d\n",
			lane_rate_kHz, ret);
		return ret;
	}

	return 0;
}

static int ad9680_set_sample_rate(struct axiadc_converter *conv,
	unsigned int sample_rate)
{
	unsigned int pll_stat;
	int ret = 0;

	/*
	 * Minimum ADC samplerate is 300 MSPS. But the minimum lane rate is
	 * 3.125 Gbps, which results in a minumum ADC samplerate of 312.5 Msps when
	 * using 4 lanes. Lower the minimum here once support for dynamic lane
	 * enable/disable has been implemented.
	 */
	sample_rate = clamp(sample_rate, 312500000U, 1000000000U);
	sample_rate = clk_round_rate(conv->clk, sample_rate);

	/* Disable link */
	ad9680_spi_write(conv->spi, 0x571, 0x15);

	clk_disable_unprepare(conv->lane_clk);
	clk_disable_unprepare(conv->sysref_clk);
	clk_disable_unprepare(conv->clk);

	ret = clk_set_rate(conv->clk, sample_rate);
	if (ret) {
		dev_err(&conv->spi->dev, "Failed to set converter clock rate to %u kHz: %d\n",
			sample_rate / 1000, ret);
		return ret;
	}

	ret = ad9680_setup_jesd204_link(conv, sample_rate);
	if (ret < 0)
		return ret;

	ret = clk_prepare_enable(conv->clk);
	if (ret) {
		dev_err(&conv->spi->dev, "Failed to enable converter clock: %d\n", ret);
		return ret;
	}
	ret = clk_prepare_enable(conv->sysref_clk);
	if (ret) {
		dev_err(&conv->spi->dev, "Failed to enable SYSREF clock: %d\n", ret);
		return ret;
	}

	// Enable link
	ad9680_spi_write(conv->spi, 0x571, 0x14);

	mdelay(20);
	pll_stat = ad9680_spi_read(conv->spi, 0x56f);

	dev_info(&conv->spi->dev, "PLL %s\n",
		 (pll_stat & 0x80) ? "LOCKED" : "UNLOCKED");

	ret = clk_prepare_enable(conv->lane_clk);
	if (ret < 0) {
		dev_err(&conv->spi->dev, "Failed to enable JESD204 link: %d\n", ret);
		return ret;
	}

	conv->adc_clk = sample_rate;

	return 0;
}

static int ad9680_request_clks(struct axiadc_converter *conv)
{
	int ret;

	conv->sysref_clk = devm_clk_get(&conv->spi->dev, "adc_sysref");
	if (IS_ERR(conv->sysref_clk)) {
		if (PTR_ERR(conv->sysref_clk) != -ENOENT)
			return PTR_ERR(conv->sysref_clk);
		conv->sysref_clk = NULL;
	} else {
		ret = clk_prepare_enable(conv->sysref_clk);
		if (ret < 0)
			return ret;
	}

	conv->clk = devm_clk_get(&conv->spi->dev, "adc_clk");
	if (IS_ERR(conv->clk) && PTR_ERR(conv->clk) != -ENOENT)
		return PTR_ERR(conv->clk);

	if (!IS_ERR(conv->clk)) {
		ret = clk_prepare_enable(conv->clk);
		if (ret < 0)
			return ret;

		conv->adc_clk = clk_get_rate(conv->clk);
	}

	conv->lane_clk = devm_clk_get(&conv->spi->dev, "jesd_adc_clk");
	if (IS_ERR(conv->lane_clk) && PTR_ERR(conv->lane_clk) != -ENOENT)
		return PTR_ERR(conv->lane_clk);

	return 0;
}

static int ad9680_setup_link(struct spi_device *spi,
	const struct ad9680_jesd204_link_config *config)
{
	unsigned int val;
	unsigned int i;
	int ret = 0;

	val = ilog2(config->octets_per_frame);
	val |= ilog2(config->num_converters) << 3;
	val |= ilog2(config->num_lanes) << 6;

944
	ret |= ad9680_spi_write(spi, 0x580, config->did);
Rene Habraken's avatar
Rene Habraken committed
945
946
947
948
	ret |= ad9680_spi_write(spi, 0x581, config->bid);

	ret = ad9680_spi_write(spi, 0x570, val); // Quick config

949
950
951
952
953
954
955
956
	for (i = 0; i < config->num_lanes; i++) {
		ret |= ad9680_spi_write(spi, 0x583 + i, config->lid[i]);

		val = config->lane_mux[i];
		val |= val << 4;
		ret |= ad9680_spi_write(spi, 0x5b2 + i + (i / 2), val);
	}

Rene Habraken's avatar
Rene Habraken committed
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
	val = config->num_lanes - 1;
	val |= config->scrambling ? 0x80 : 0x00;
	ret |= ad9680_spi_write(spi, 0x58b, val);

	ret |= ad9680_spi_write(spi, 0x58d, config->frames_per_multiframe - 1);
	ret |= ad9680_spi_write(spi, 0x58f, config->converter_resolution - 1);

	val = config->bits_per_sample - 1;
	val |= config->subclass ? 0x20 : 0x00;
	ret |= ad9680_spi_write(spi, 0x590, val);

	/* Disable SYSREF */
	ret |= ad9680_spi_write(spi, 0x120, 0x00);

	ret |= ad9680_spi_write(spi, 0x121, 0x0f);

	switch (config->sysref.mode) {
	case AD9680_SYSREF_CONTINUOUS:
		val = 0x02;
		break;
	case AD9680_SYSREF_ONESHOT:
		val = 0x04;
		break;
	default:
		val = 0x00;
		break;
	}

	if (config->sysref.capture_falling_edge)
		val |= 0x08;

	if (config->sysref.valid_falling_edge)
		val |= 0x10;
	ret |= ad9680_spi_write(spi, 0x120, val);

	return ret;
}

static int ad9680_setup(struct spi_device *spi, bool ad9234)
{
	struct axiadc_converter *conv = spi_get_drvdata(spi);
	struct ad9680_jesd204_link_config link_config;
	unsigned int pll_stat;
	unsigned int i;
For faster browsing, not all history is shown. View entire blame