zynqmp-zu7cg-rev1-ad9694.dts 15.6 KB
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/*
 * dts file from: FMCDAQ3 on Xilinx ZynqMP ZCU102 Rev 1.0
 *            to: GRANDproto_v1 Xilinx ZynqMP ZU7CG Rev 1.0
 *
 * Copyright (C) 2018 Analog Devices Inc.
 * Modified by R. Habraken: Radboud University Nijmegen
 *
 * Licensed under the GPL-2.
 */

/* i2c and axi-bus*/


#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/iio/frequency/ad9528.h>
#include "zynqmp-zcu102-rev1.0.dts"
/ {

    /* U-BOOT ARGUMENTS AND ROOTFS SETTINGS */
    chosen  {
        bootargs = "console=ttyPS0,115200 earlyprintk clk_ignore_unused root=mtd:jffs2 rw rootfstype=jffs2";
        stdout-path = "serial0:115200n8";
        xlnx,eeprom = &eeprom;
        };
    
    /* XTAL FOR Si5340 */
    xtal48MHz: xtal_48_clock {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
         clock-frequency = <48000000>;
    };

    /* AXI INTERFACE */
    fpga_axi: fpga-axi@0 {
        interrupt-parent = <&gic>;
        compatible = "simple-bus";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        ranges = <0 0 0 0xffffffff>;

        rx_dma: rx-dmac@9c400000 {
            #dma-cells = <1>;
            compatible = "adi,axi-dmac-1.00.a";
            reg = <0x9c400000 0x10000>;
            interrupts = <0 109 0>;
            clocks = <&clk 71>;

            adi,channels {
                #size-cells = <0>;
                #address-cells = <1>;

                dma-channel@0 {
                    reg = <0>;
                    adi,source-bus-width = <64>;
                    adi,source-bus-type = <1>;
                    adi,destination-bus-width = <64>;
                    adi,destination-bus-type = <0>;
                };
            };
        };

        axi_ad9694_core: axi-ad9694-hpc@84a10000 {
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            compatible = "adi,axi-ad9694-1.0";
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            reg = <0x84a10000 0x10000>;
            dmas = <&rx_dma 0>;
            dma-names = "rx";
            spibus-connected = <&adc0_ad9694>;
        };

        axi_ad9694_jesd: axi-jesd204-rx@84aa0000 {
            compatible = "adi,axi-jesd204-rx-1.0";
            reg = <0x84aa0000 0x4000>;
            interrupts = <0 107 0>;

            clocks = <&clk 71>, <&axi_ad9694_adxcvr 1>, <&axi_ad9694_adxcvr 0>;
            clock-names = "s_axi_aclk", "device_clk", "lane_clk";
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            adi,subclass = <0>;
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            adi,frames-per-multiframe = <32>;
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            adi,octets-per-frame = <2>;
            adi,converter-resolution = <16>;
            adi,bits-per-sample = <16>;
            adi,converters-per-device = <4>;      
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            #clock-cells = <0>;
            clock-output-names = "jesd_adc_lane_clk";
        };

        axi_ad9694_adxcvr: axi-adxcvr-rx@84a50000 {
            compatible = "adi,axi-adxcvr-1.0";
            reg = <0x84a50000 0x1000>;

            clocks = <&si5340 0 2>;
            clock-names = "conv";
            
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            adi,sys-clk-select = <3>;
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            adi,out-clk-select = <3>;
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            adi,use-lpm-enable;
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            /* RH: Change to QPLL see zynqMP datasheet max line rate CPLL=8.5Gb/s */
            /* adi,use-cpll-enable; */
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            #clock-cells = <1>;
            clock-output-names = "adc_gt_clk", "rx_out_clk";
        };

        axi_sysid_0: axi-sysid-0@85000000 {
            compatible = "adi,axi-sysid-1.00.a";
            reg = <0x85000000 0x10000>;
        };
    };
};
/* END AXI INTERFACE */


&spi0 {
    status = "okay";
    num-cs = <1>;

    adc0_ad9694: ad9694@0 {
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        compatible = "adi,ad9694";
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        reg = <0>;
        spi-max-frequency = <10000000>;
        adi,spi-3wire-enable;
        spi-cpol;
        spi-cpha;

        /* gpio =       78 + 38||35||34 */
        powerdown-gpios = <&gpio 116 0>;
        fastdetect-a-gpios = <&gpio 113 0>;
        fastdetect-b-gpios = <&gpio 114 0>;
    
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        clocks =  <&axi_ad9694_jesd>, <&si5340 0 3>;
        clock-names = "jesd_adc_clk", "adc_clk";
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        /*assigned-clock-parents = <&si5340 1 3>; */
        /*assigned-clock-rates   = <1000000000>;  */
    };
};

&qspi {
    status = "okay";
    is-dual = <1>;
    has-io-mode = <1>;
    /delete-node/ flash@0;
    flash@0 {
        compatible = "micron,m25p80", "spi-flash", "n25q512a"; /* dual 512Mb, 1Gb total */
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        reg = <0x0>;
        spi-tx-bus-width = <0x1>;
        spi-rx-bus-width = <0x4>; 
        spi-max-frequency = <0x66ff300>; 
        partition@boot {
            label = "boot";
            reg = <0x0 0x1e00000>;
        };

        partition@bootenv {
            label = "bootenv";
            reg = <0x1e00000 0x40000>;
        };

        partition@kernel {
            label = "kernel";
            reg = <0x1e40000 0x2400000>;
        };

        partition@jffs2 {
            label = "jffs2";
            reg = <0x4240000 0x2EE0000>;
        };
        partition@spare {
            label = "spare";
            reg = <0x7120000 0x20000>;
        };      
    };
};


/* I2C0 BUS */
&i2c0 {
    status = "okay";
    clock-frequency = <400000>;
    pinctrl-names = "default", "gpio";
    pinctrl-0 = <&pinctrl_i2c0_default>;
    pinctrl-1 = <&pinctrl_i2c0_gpio>;
    scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
    sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
    /delete-node/ gpio@20;
    /delete-node/ gpio@21;
    /delete-node/ i2c-mux@75;

    /* EEPROM */
    eeprom: eeprom@54 {
        compatible = "at,24c08","atmel,24c08";
        pagesize = <16>;
        reg = <0x54>;
    };

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    /* Programmable clock */
    si5340: si5340@76 {
        reg = <0x76>;
        compatible = "silabs,si5340";
        #clock-cells = <2>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&xtal48MHz>;
        clock-names = "xtal";
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        silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
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        silabs,pll-m-den = <48>;

        assigned-clocks = <&si5340 1 0>,
                          <&si5340 1 1>,
                          <&si5340 1 2>,
                          <&si5340 1 3>,
                          <&si5340 0 0>,
                          <&si5340 0 1>,
                          <&si5340 0 2>,
                          <&si5340 0 3>;
        assigned-clock-parents = <0>, <0>, <0>, <0>,
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                          <&si5340 1 1>, /* output 0 uses PLL 1 */
                          <&si5340 1 2>, /* output 1 uses PLL 2 */
                          <&si5340 1 0>, /* output 2 uses PLL 0 */
                          <&si5340 1 0>; /* output 3 uses PLL 0 */
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        assigned-clock-rates = <2000000000>, /* wat betekent dit en waar komt deze waarde vandaan? 0 */
                          <162000000>,
                          <600000000>,
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                          <0>,
                          <27000000>, /* out 0 */
                          <300000000>,
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                          <250000000>, /*250 MHz */
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                          <500000000>; /*500 MHz */
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        out@1 {
            /* PL_DDR_CLK (300MHz) */
            reg = <1>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };

        out@2 {
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            /* MGTREFCLK0 RX refclk (250MHz) */
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            reg = <2>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };

        out@3 {
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            /* ADC_REF_CLK (500MHz) */
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            reg = <3>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };
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    };

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    /* MAXIM_PMBUS - 00 */
    u88: max15301@0A { /* u88 */
        compatible = "maxim,max15301";
        reg = <0x0A>;
    };
    u91: max15303@0B { /* u91 */
        compatible = "maxim,max15303";
        reg = <0x0B>;
    };
    u81: max15303@10 { /* u81 */
        compatible = "maxim,max15303";
        reg = <0x10>;
    };
    u79: max15301@13 { /* u79 */
        compatible = "maxim,max15301";
        reg = <0x13>;
    };
    u77: max15303@14 { /* u77 */
        compatible = "maxim,max15303";
        reg = <0x14>;
    };
    u75: max15303@15 { /* u75 */
        compatible = "maxim,max15303";
        reg = <0x15>;
    };
    u71: max15303@16 { /* u71 */
        compatible = "maxim,max15303";
        reg = <0x16>;
    };
    u73: max15303@17 { /* u73 */
        compatible = "maxim,max15303";
        reg = <0x17>;
    };
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    u68: max15301@1a { /* u68 */
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        compatible = "maxim,max15301";
        reg = <0x1a>;
    };
    u50: max15303@1d { /* u50 */
        compatible = "maxim,max15303";
        reg = <0x1d>;
    };
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    u52: max20751@72 { /* u52 */
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        compatible = "maxim,max20751";
        reg = <0x72>;
    };
    u54: max20751@73 { /* u54 */
        compatible = "maxim,max20751";
        reg = <0x73>;
    };
};
/*END I2C0 BUS */


/* DEVICE TREE DISABLES */
&i2c1 {
    status = "disabled";

        /delete-node/ i2c-mux@74;
        /delete-node/ i2c-mux@75;
};

&sdhci1 {
 status = "disabled";
};

&pcie {
 status = "disabled";
};

&sata {
 status = "disabled";
};

&can1 {
 status = "disabled";
};

&zynqmp_dpsub {
 status = "disabled";
};

&usb0 {
 status = "disabled";
};

&gpu {
 status = "disabled";
};

&xlnx_dpdma {
 status = "disabled";
};

&spi0 {
    status = "okay";
};

&spi1 {
    status = "disabled";
};

&uart0 {
    status = "okay";
};

&uart1 {
    status = "okay";
};

/* PINCTRL SETTINGS */
&pinctrl0 {
    status = "okay";
    pinctrl_i2c0_default: i2c0-default {
        mux {
            groups = "i2c0_3_grp";
            function = "i2c0";
        };

        conf {
            groups = "i2c0_3_grp";
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c0_gpio: i2c0-gpio {
        mux {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c1_default: i2c1-default {
        mux {
            groups = "i2c1_4_grp";
            function = "i2c1";
        };

        conf {
            groups = "i2c1_4_grp";
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c1_gpio: i2c1-gpio {
        mux {
            groups = "gpio0_16_grp", "gpio0_17_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_16_grp", "gpio0_17_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c0_gpio: i2c0-gpio {
        mux {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };
    pinctrl_uart0_default: uart0-default {
        mux {
            groups = "uart0_4_grp";
            function = "uart0";
        };

        conf {
            groups = "uart0_4_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO18";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO19";
            bias-disable;
        };
    };

    pinctrl_uart1_default: uart1-default {
        mux {
            groups = "uart1_5_grp";
            function = "uart1";
        };

        conf {
            groups = "uart1_5_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO21";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO20";
            bias-disable;
        };
    };

    pinctrl_usb0_default: usb0-default {
        mux {
            groups = "usb0_0_grp";
            function = "usb0";
        };

        conf {
            groups = "usb0_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO52", "MIO53", "MIO55";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
                   "MIO60", "MIO61", "MIO62", "MIO63";
            bias-disable;
        };
    };

    pinctrl_gem3_default: gem3-default {
        mux {
            function = "ethernet3";
            groups = "ethernet3_0_grp";
        };

        conf {
            groups = "ethernet3_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
                                    "MIO75";
            bias-high-impedance;
            low-power-disable;
        };

        conf-tx {
            pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
                                    "MIO69";
            bias-disable;
            low-power-enable;
        };

        mux-mdio {
            function = "mdio3";
            groups = "mdio3_0_grp";
        };

        conf-mdio {
            groups = "mdio3_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
            bias-disable;
        };
    };

    pinctrl_can1_default: can1-default {
        mux {
            function = "can1";
            groups = "can1_6_grp";
        };

        conf {
            groups = "can1_6_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO25";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO24";
            bias-disable;
        };
    };

    pinctrl_sdhci1_default: sdhci1-default {
        mux {
            groups = "sdio1_0_grp";
            function = "sdio1";
        };

        conf {
            groups = "sdio1_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
            bias-disable;
        };

        mux-cd {
            groups = "sdio1_cd_0_grp";
            function = "sdio1_cd";
        };

        conf-cd {
            groups = "sdio1_cd_0_grp";
            bias-high-impedance;
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        mux-wp {
            groups = "sdio1_wp_0_grp";
            function = "sdio1_wp";
        };

        conf-wp {
            groups = "sdio1_wp_0_grp";
            bias-high-impedance;
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_gpio_default: gpio-default {
        mux-sw {
            function = "gpio0";
            groups = "gpio0_22_grp", "gpio0_23_grp";
        };

        conf-sw {
            groups = "gpio0_22_grp", "gpio0_23_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        mux-msp {
            function = "gpio0";
            groups = "gpio0_13_grp", "gpio0_38_grp";
        };

        conf-msp {
            groups = "gpio0_13_grp", "gpio0_38_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-pull-up {
            pins = "MIO22", "MIO23";
            bias-pull-up;
        };

        conf-pull-none {
            pins = "MIO13", "MIO38";
            bias-disable;
        };
    };
};