Commit 04079514 authored by Rene Habraken's avatar Rene Habraken
Browse files

with added debug probes, device in IIO_INFO

parent bc2279f5
......@@ -285,4 +285,9 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
CONFIG_USER_LAYER_2=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"
......@@ -82,7 +82,7 @@ unsigned long psu_pll_init_data(void)
* Register : RPLL_CFG @ 0XFF5E0034
 
* PLL loop filter resistor control
* PSU_CRL_APB_RPLL_CFG_RES 0x4
* PSU_CRL_APB_RPLL_CFG_RES 0x2
 
* PLL charge pump control
* PSU_CRL_APB_RPLL_CFG_CP 0x3
......@@ -97,9 +97,9 @@ unsigned long psu_pll_init_data(void)
* PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
 
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C64U)
* (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C64U);
PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
/*##################################################################### */
 
/*
......@@ -114,16 +114,16 @@ unsigned long psu_pll_init_data(void)
* PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
 
* The integer portion of the feedback divider to the PLL
* PSU_CRL_APB_RPLL_CTRL_FBDIV 0x6f
* PSU_CRL_APB_RPLL_CTRL_FBDIV 0x4a
 
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
 
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00016F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014A00U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00016F00U);
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00014A00U);
/*##################################################################### */
 
/*
......@@ -212,14 +212,14 @@ unsigned long psu_pll_init_data(void)
* Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048
 
* Divisor value for this clock.
* PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3
* PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2
 
* Control for a clock that will be generated in the LPD, but used in the F
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U)
* (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U)
*/
PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET,
0x00003F00U, 0x00000300U);
0x00003F00U, 0x00000200U);
/*##################################################################### */
 
/*
......@@ -1042,7 +1042,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0x5
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1050,10 +1050,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010F02U)
* (OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010502U)
*/
PSU_Mask_Write(CRL_APB_SPI0_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F02U);
0x013F3F07U, 0x01010502U);
/*##################################################################### */
 
/*
......
......@@ -11,7 +11,7 @@ set psu_pll_init_data {
# Register : RPLL_CFG @ 0XFF5E0034</p>
 
# PLL loop filter resistor control
# PSU_CRL_APB_RPLL_CFG_RES 0x4
# PSU_CRL_APB_RPLL_CFG_RES 0x2
 
# PLL charge pump control
# PSU_CRL_APB_RPLL_CFG_CP 0x3
......@@ -26,8 +26,8 @@ set psu_pll_init_data {
# PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
 
# Helper data. Values are to be looked up in a table from Data Sheet
#(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C64U) */
mask_write 0XFF5E0034 0xFE7FEDEF 0x7E4B0C64
#(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) */
mask_write 0XFF5E0034 0xFE7FEDEF 0x7E4B0C62
# : UPDATE FB_DIV
# Register : RPLL_CTRL @ 0XFF5E0030</p>
 
......@@ -37,15 +37,15 @@ set psu_pll_init_data {
# PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
 
# The integer portion of the feedback divider to the PLL
# PSU_CRL_APB_RPLL_CTRL_FBDIV 0x6f
# PSU_CRL_APB_RPLL_CTRL_FBDIV 0x4a
 
# This turns on the divide by 2 that is inside of the PLL. This does not c
# hange the VCO frequency, just the output frequency
# PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
 
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00016F00U) */
mask_write 0XFF5E0030 0x00717F00 0x00016F00
#(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014A00U) */
mask_write 0XFF5E0030 0x00717F00 0x00014A00
# : BY PASS PLL
# Register : RPLL_CTRL @ 0XFF5E0030</p>
 
......@@ -99,12 +99,12 @@ set psu_pll_init_data {
# Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048</p>
 
# Divisor value for this clock.
# PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3
# PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2
 
# Control for a clock that will be generated in the LPD, but used in the F
# PD as a clock source for the peripheral clock muxes.
#(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) */
mask_write 0XFF5E0048 0x00003F00 0x00000300
#(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) */
mask_write 0XFF5E0048 0x00003F00 0x00000200
# : RPLL FRAC CFG
# : SYSMON CLOCK PRESET TO RPLL AGAIN TO AVOID GLITCH WHEN NEXT IOPLL WILL BE PUT IN BYPASS MODE
# Register : AMS_REF_CTRL @ 0XFF5E0108</p>
......@@ -671,7 +671,7 @@ set psu_clock_init_data {
# PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 0x1
 
# 6 bit divider
# PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0xf
# PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0x5
 
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -679,8 +679,8 @@ set psu_clock_init_data {
# PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL 0x2
 
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010F02U) */
mask_write 0XFF5E007C 0x013F3F07 0x01010F02
#(OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010502U) */
mask_write 0XFF5E007C 0x013F3F07 0x01010502
# Register : CPU_R5_CTRL @ 0XFF5E0090</p>
 
# Turing this off will shut down the OCM, some parts of the APM, and preve
......
......@@ -69,7 +69,7 @@ unsigned long psu_pll_init_data(void)
* Register : RPLL_CFG @ 0XFF5E0034
 
* PLL loop filter resistor control
* PSU_CRL_APB_RPLL_CFG_RES 0x4
* PSU_CRL_APB_RPLL_CFG_RES 0x2
 
* PLL charge pump control
* PSU_CRL_APB_RPLL_CFG_CP 0x3
......@@ -84,9 +84,9 @@ unsigned long psu_pll_init_data(void)
* PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
 
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C64U)
* (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C64U);
PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
/*##################################################################### */
 
/*
......@@ -101,16 +101,16 @@ unsigned long psu_pll_init_data(void)
* PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
 
* The integer portion of the feedback divider to the PLL
* PSU_CRL_APB_RPLL_CTRL_FBDIV 0x6f
* PSU_CRL_APB_RPLL_CTRL_FBDIV 0x4a
 
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
 
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00016F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014A00U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00016F00U);
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00014A00U);
/*##################################################################### */
 
/*
......@@ -199,14 +199,14 @@ unsigned long psu_pll_init_data(void)
* Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048
 
* Divisor value for this clock.
* PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3
* PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2
 
* Control for a clock that will be generated in the LPD, but used in the F
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U)
* (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U)
*/
PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET,
0x00003F00U, 0x00000300U);
0x00003F00U, 0x00000200U);
/*##################################################################### */
 
/*
......@@ -1029,7 +1029,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0x5
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1037,10 +1037,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010F02U)
* (OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010502U)
*/
PSU_Mask_Write(CRL_APB_SPI0_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F02U);
0x013F3F07U, 0x01010502U);
/*##################################################################### */
 
/*
......
......@@ -83,7 +83,7 @@ ad_ip_parameter util_grand_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_grand_xcvr CONFIG.QPLL_FBDIV_RATIO 1
ad_ip_parameter util_grand_xcvr CONFIG.QPLL_FBDIV 0x30; # 20
ad_ip_parameter util_grand_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_grand_xcvr CONFIG.TX_OUT_DIV 1
#ad_ip_parameter util_grand_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_grand_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
ad_ip_parameter util_grand_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020
......@@ -92,7 +92,7 @@ ad_connect $sys_cpu_clk util_grand_xcvr/up_clk
# reference clocks & resets
create_bd_port -dir I tx_ref_clk_0
#create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
#Prevent error on util_grand_xcvr for missing clock input.
......
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