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Rene Habraken
GRAND_V1
Commits
0805abe4
Commit
0805abe4
authored
Jul 22, 2020
by
Rene Habraken
Browse files
debugging 4 converters for ad9694
parent
cf4d65ee
Changes
1
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Inline
Side-by-side
meta-adi/grand_zcu7/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/ad9680_debug.c
View file @
0805abe4
...
...
@@ -802,7 +802,7 @@ static int ad9680_setup_jesd204_link(struct axiadc_converter *conv,
int
ret
;
sysref_rate
=
DIV_ROUND_CLOSEST
(
sample_rate
,
32
);
lane_rate_kHz
=
DIV_ROUND_CLOSEST
(
sample_rate
,
10
0
);
lane_rate_kHz
=
DIV_ROUND_CLOSEST
(
sample_rate
,
5
0
);
if
(
lane_rate_kHz
<
3125000
||
lane_rate_kHz
>
12500000
)
{
dev_err
(
&
conv
->
spi
->
dev
,
"Lane rate %lu Mbps out of bounds. Must be between 3125 and 12500 Mbps"
,
...
...
@@ -941,19 +941,10 @@ static int ad9680_setup_link(struct spi_device *spi,
val
|=
ilog2
(
config
->
num_converters
)
<<
3
;
val
|=
ilog2
(
config
->
num_lanes
)
<<
6
;
ret
|=
ad9680_spi_write
(
spi
,
0x580
,
config
->
did
);
ret
|=
ad9680_spi_write
(
spi
,
0x581
,
config
->
bid
);
ret
=
ad9680_spi_write
(
spi
,
0x570
,
val
);
// Quick config
for
(
i
=
0
;
i
<
config
->
num_lanes
;
i
++
)
{
ret
|=
ad9680_spi_write
(
spi
,
0x583
+
i
,
config
->
lid
[
i
]);
val
=
config
->
lane_mux
[
i
];
val
|=
val
<<
4
;
ret
|=
ad9680_spi_write
(
spi
,
0x5b2
+
i
+
(
i
/
2
),
val
);
}
val
=
config
->
num_lanes
-
1
;
val
|=
config
->
scrambling
?
0x80
:
0x00
;
ret
|=
ad9680_spi_write
(
spi
,
0x58b
,
val
);
...
...
@@ -1038,7 +1029,7 @@ static int ad9680_setup(struct spi_device *spi, bool ad9234)
link_config
.
lane_mux
[
i
]
=
i
;
}
link_config
.
num_converters
=
2
;
link_config
.
octets_per_frame
=
1
;
link_config
.
octets_per_frame
=
2
;
link_config
.
frames_per_multiframe
=
32
;
link_config
.
converter_resolution
=
ad9234
?
12
:
14
;
link_config
.
bits_per_sample
=
16
;
...
...
@@ -1115,13 +1106,14 @@ static int ad9694_setup_jesd204_link(struct axiadc_converter *conv,
sysref_rate
=
DIV_ROUND_CLOSEST
(
sample_rate
,
128
);
else
sysref_rate
=
DIV_ROUND_CLOSEST
(
sample_rate
,
32
);
lane_rate_kHz
=
DIV_ROUND_CLOSEST
(
sample_rate
,
10
0
);
dev_
err
(
&
conv
->
spi
->
dev
,
"RH: Lane rate %lu Mbps is"
,
lane_rate_kHz
=
DIV_ROUND_CLOSEST
(
sample_rate
,
5
0
);
dev_
info
(
&
conv
->
spi
->
dev
,
"RH: Lane rate %lu Mbps is"
,
lane_rate_kHz
/
1000
);
dev_err
(
&
conv
->
spi
->
dev
,
"RH: sysref rate %lu Mbps is"
,
sysref_rate
);
dev_info
(
&
conv
->
spi
->
dev
,
"RH: Sysref rate %lu Mbps is"
,
sysref_rate
);
dev_info
(
&
conv
->
spi
->
dev
,
"RH: Sample rate %i Mbps is"
,
sample_rate
);
if
(
lane_rate_kHz
<
1687500
||
lane_rate_kHz
>
15000000
)
{
dev_err
(
&
conv
->
spi
->
dev
,
"Lane rate %lu Mbps out of bounds. Must be between 1687.5 and 15000 Mbps"
,
lane_rate_kHz
/
1000
);
...
...
@@ -1180,21 +1172,21 @@ static int ad9694_setup(struct spi_device *spi)
ad9680_spi_write
(
spi
,
0x000
,
0x81
);
/* RESET */
mdelay
(
5
);
/* Configure A/B */
/* Configure A/B
and C/D
*/
ret
|=
ad9680_spi_write
(
spi
,
0x009
,
0x03
);
/* select pair A/B */
ret
|=
ad9680_spi_write
(
spi
,
0x008
,
0x03
);
/* select both channels */
ret
|=
ad9680_spi_write
(
spi
,
0x108
,
0x00
);
/* Clock divider = 1 */
memset
(
&
link_config
,
sizeof
(
link_config
),
0x00
);
link_config
.
did
=
0
;
link_config
.
bid
=
0
;
link_config
.
num_lanes
=
4
;
for
(
i
=
0
;
i
<
link_config
.
num_lanes
;
i
++
)
{
link_config
.
lid
[
i
]
=
i
;
link_config
.
lane_mux
[
i
]
=
i
;
}
link_config
.
num_converters
=
4
;
// link_config.did = 0;
link_config
.
num_lanes
=
2
;
//for (i = 0; i < link_config.num_lanes; i++) {
//link_config.lid[i] = i;
//link_config.lane_mux[i] = i;
//}
link_config
.
num_converters
=
2
;
link_config
.
octets_per_frame
=
2
;
link_config
.
frames_per_multiframe
=
32
;
link_config
.
converter_resolution
=
14
;
...
...
@@ -1219,6 +1211,67 @@ static int ad9694_setup(struct spi_device *spi)
ret
|=
ad9680_spi_write
(
spi
,
0x001
,
0x02
);
/* datapath soft reset */
mdelay
(
1
);
///* Configure A */
ret
|=
ad9680_spi_write
(
spi
,
0x009
,
0x01
);
/* select link A/B (0x01), select link C/D (0x10) */
ret
|=
ad9680_spi_write
(
spi
,
0x008
,
0x01
);
/* select conv A/C (0x01), select conv B/D (0x10) */
link_config
.
did
=
0
;
link_config
.
lid
[
0
]
=
0
;
link_config
.
lane_mux
[
0
]
=
0
;
ret
=
ad9680_spi_write
(
spi
,
0x580
,
0x0
);
/*config->did); */
ret
|=
ad9680_spi_write
(
spi
,
0x583
,
0x0
);
/*config->lid[0]); */
ret
|=
ad9680_spi_write
(
spi
,
0x5b2
,
0x0
);
/*config->lane_mux[0]); */
ret
|=
ad9680_spi_write
(
spi
,
0x001
,
0x02
);
/* datapath soft reset */
ret
=
ad9680_spi_read
(
conv
->
spi
,
0x58b
);
/*read lanes per link */
mdelay
(
1
);
dev_info
(
&
conv
->
spi
->
dev
,
"RH: config ADC A done %i ret is"
,
ret
);
///* Configure B */
ret
|=
ad9680_spi_write
(
spi
,
0x009
,
0x01
);
/* select link A/B (0x01), select link C/D (0x10) */
ret
|=
ad9680_spi_write
(
spi
,
0x008
,
0x02
);
/* select conv A/C (0x01), select conv B/D (0x10) */
ret
=
ad9680_spi_write
(
spi
,
0x580
,
0x1
);
/*config->did); */
ret
|=
ad9680_spi_write
(
spi
,
0x585
,
0x1
);
/*config->lid[0]); */
ret
|=
ad9680_spi_write
(
spi
,
0x5b3
,
0x1
);
/*config->lane_mux[0]); */
ret
|=
ad9680_spi_write
(
spi
,
0x001
,
0x02
);
/* datapath soft reset */
ret
=
ad9680_spi_read
(
conv
->
spi
,
0x58b
);
/*read lanes per link */
mdelay
(
1
);
dev_info
(
&
conv
->
spi
->
dev
,
"RH: config ADC B done %i ret is"
,
ret
);
///* Configure C */
ret
|=
ad9680_spi_write
(
spi
,
0x009
,
0x02
);
/* select link A/B (0x01), select link C/D (0x10) */
ret
|=
ad9680_spi_write
(
spi
,
0x008
,
0x01
);
/* select conv A/C (0x01), select conv B/D (0x10) */
ret
=
ad9680_spi_write
(
spi
,
0x580
,
0x2
);
/*config->did); */
ret
|=
ad9680_spi_write
(
spi
,
0x583
,
0x2
);
/*config->lid[0]); */
ret
|=
ad9680_spi_write
(
spi
,
0x5b2
,
0x2
);
/*config->lane_mux[0]); */
ret
|=
ad9680_spi_write
(
spi
,
0x001
,
0x02
);
/* datapath soft reset */
ret
=
ad9680_spi_read
(
conv
->
spi
,
0x58b
);
/*read lanes per link */
mdelay
(
1
);
dev_info
(
&
conv
->
spi
->
dev
,
"RH: config ADC C done %i ret is"
,
ret
);
///* Configure D */
ret
|=
ad9680_spi_write
(
spi
,
0x009
,
0x02
);
/* select link A/B (0x01), select link C/D (0x10) */
ret
|=
ad9680_spi_write
(
spi
,
0x008
,
0x02
);
/* select conv A/C (0x01), select conv B/D (0x10) */
ret
=
ad9680_spi_write
(
spi
,
0x580
,
0x3
);
/*config->did); */
ret
|=
ad9680_spi_write
(
spi
,
0x585
,
0x3
);
/*config->lid[0]); */
ret
|=
ad9680_spi_write
(
spi
,
0x5b3
,
0x3
);
/*config->lane_mux[0]); */
ret
|=
ad9680_spi_write
(
spi
,
0x001
,
0x02
);
/* datapath soft reset */
ret
=
ad9680_spi_read
(
conv
->
spi
,
0x58b
);
/*read lanes per link */
mdelay
(
1
);
dev_info
(
&
conv
->
spi
->
dev
,
"RH: config ADC D done %i ret is"
,
ret
);
ret
=
ad9694_setup_jesd204_link
(
conv
,
conv
->
adc_clk
);
if
(
ret
<
0
)
return
ret
;
...
...
@@ -1265,7 +1318,7 @@ static int ad9694_setup(struct spi_device *spi)
return
ret
;
}
schedule_delayed_work
(
&
conv
->
watchdog_work
,
HZ
);
//
schedule_delayed_work(&conv->watchdog_work, HZ);
conv
->
sample_rate_read_only
=
true
;
...
...
@@ -1364,6 +1417,9 @@ static int ad9680_write_raw(struct iio_dev *indio_dev,
}
ret
=
clk_set_rate
(
conv
->
clk
,
r_clk
);
dev_info
(
&
conv
->
spi
->
dev
,
"RH: AD9694 sample clk %ul
\n
"
,
r_clk
);
if
(
ret
<
0
)
return
ret
;
break
;
...
...
@@ -1440,7 +1496,7 @@ static int ad9680_probe(struct spi_device *spi)
conv
->
adc_clkscale
.
mult
=
1
;
conv
->
adc_clkscale
.
div
=
1
;
INIT_DELAYED_WORK
(
&
conv
->
watchdog_work
,
ad9694_serdes_pll_watchdog
);
//
INIT_DELAYED_WORK(&conv->watchdog_work, ad9694_serdes_pll_watchdog);
spi_set_drvdata
(
spi
,
conv
);
conv
->
spi
=
spi
;
...
...
@@ -1529,7 +1585,7 @@ static int ad9680_remove(struct spi_device *spi)
{
struct
axiadc_converter
*
conv
=
spi_get_drvdata
(
spi
);
cancel_delayed_work_sync
(
&
conv
->
watchdog_work
);
//
cancel_delayed_work_sync(&conv->watchdog_work);
clk_disable_unprepare
(
conv
->
clk
);
return
0
;
...
...
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