Commit 1951b574 authored by Rene Habraken's avatar Rene Habraken
Browse files

modified pll settings, still hangs at boot

parent 4705d96e
......@@ -204,9 +204,8 @@
clocks = <&xtal48MHz>;
clock-names = "xtal";
silabs,pll-m-num = <13600>; /* PLL at 13.6 GHz */
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
silabs,pll-m-den = <48>;
silabs,reprogram; /* Reprogram to allow AD driver setting the lane rate */
assigned-clocks = <&si5340 1 0>,
<&si5340 1 1>,
......@@ -217,10 +216,10 @@
<&si5340 0 2>,
<&si5340 0 3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&si5340 1 0>,
<&si5340 1 0>,
<&si5340 1 0>,
<&si5340 1 0>;
<&si5340 1 1>, /* output 0 uses PLL 1 */
<&si5340 1 2>, /* output 1 uses PLL 2 */
<&si5340 1 0>, /* output 2 uses PLL 0 */
<&si5340 1 0>; /* output 3 uses PLL 0 */
assigned-clock-rates = <400000000>, /* wat betekent dit en waar komt deze waarde vandaan? 0 */
<0>,
<0>,
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment