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Commit 3428687d authored by Rene Habraken's avatar Rene Habraken
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cpll to qpll, added debug patches, connected syncA/B/C/D -part2

parent 911766b0
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hardware/BoardFiles/zu7cg/production/1.0/board.xml
View file @ 3428687d
......@@ -301,10 +301,10 @@
<description>PL I2C0</description>
</component>
<component name="ddr4_sdram" display_name="DDR4 SDRAM" type="chip" sub_type="ddr" major_group="External Memory" part_name="MT40A256M16GE-075E" vendor="Micron" spec_url="https://www.micron.com/parts/dram/ddr4-sdram/mt40a256m16ge-075e">
<description>2GB DDR4 SDRAM memory SODIMM</description>
<description>4Gbit DDR4 SDRAM memory for PL</description>
<parameters>
<parameter name="ddr_type" value="ddr4"/>
<parameter name="size" value="2GB"/>
<parameter name="size" value="4Gb"/>
</parameters>
</component>
<component name="reset" display_name="FPGA Reset" type="chip" sub_type="system_reset" major_group="Reset" part_name="TL3301EP100QG" vendor="ESwitch">
......
meta-adi/grand_zcu7/project-spec/configs/config
View file @ 3428687d
......@@ -123,9 +123,7 @@ CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0"
#
# SD/SDIO Settings
#
CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y
CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT=y
#
# RTC Settings
......@@ -140,7 +138,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y
# boot image settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_PART_NAME="boot"
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
......@@ -149,7 +146,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
# u-boot env partition settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
......@@ -157,7 +153,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
# kernel image settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_PART_NAME="kernel"
......@@ -176,7 +171,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2"
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
......
meta-adi/grand_zcu7/project-spec/configs/config.old
View file @ 3428687d
......@@ -291,4 +291,6 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
CONFIG_USER_LAYER_2=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"
meta-adi/grand_zcu7/project-spec/meta-user/conf/layer.conf
View file @ 3428687d
......@@ -7,4 +7,4 @@ BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
BBFILE_COLLECTIONS += "meta-user"
BBFILE_PATTERN_meta-user = "^${LAYERDIR}/"
BBFILE_PRIORITY_meta-user = "6"
BBFILE_PRIORITY_meta-user = "7"
meta-adi/meta-adi-xilinx/recipes-bsp/device-tree/files/zynqmp-zu7cg-rev1-ad9694.dts
View file @ 3428687d
......@@ -92,10 +92,11 @@
clocks = <&si5340 0 2>;
clock-names = "conv";
adi,sys-clk-select = <0>;
adi,sys-clk-select = <3>;
adi,out-clk-select = <4>;
adi,use-lpm-enable;
adi,use-cpll-enable;
/* RH: Change to QPLL see zynqMP datasheet max line rate CPLL=8.5Gb/s */
/* adi,use-cpll-enable; */
#clock-cells = <1>;
clock-output-names = "adc_gt_clk", "rx_out_clk";
......@@ -226,7 +227,7 @@
<0>,
<27000000>, /* out 0 */
<300000000>,
<31250000>, /*31.25 MHz */
<500000000>, /*500 MHz */
<1000000000>;
out@1 {
......@@ -239,7 +240,7 @@
};
out@2 {
/* MGTREFCLK0 RX refclk (???MHz) */
/* MGTREFCLK0 RX refclk (500MHz) */
reg = <2>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
......
meta-adi/meta-adi-xilinx/recipes-kernel/linux/linux-adi.inc
View file @ 3428687d
......@@ -19,15 +19,12 @@ do_configure_prepend_microblaze() {
sed -i 's,CONFIG_INITRAMFS_SOURCE=.*,,' ${B}/.config
}
SRC_URI += "file://user_2020-03-18-17-15-00.cfg \
"
#SRC_URI_append += "
#file://0001-added-SiLabs-Si5341-driver.patch \
#file://0001-enabled-DEBUG-in-ad9680-driver.patch \
#file://0001-added-Si5341-driver.patch \
#file://user_2020-05-7-17-9-00.cfg \
#file://user_2020-05-13-20-56-00.cfg \
#SRC_URI += "file://user_2020-03-18-17-15-00.cfg \
#"
FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
#
#SRC_URI_append += " \
#file://0001-debug-txcvr.patch \
#file://0001-debug-ad9680.patch \
#"
#
#FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
projects/grand/common/grand_bd.tcl
View file @ 3428687d
......@@ -44,7 +44,7 @@ set adc_dma_data_width 64
ad_ip_instance axi_adxcvr axi_ad9694_xcvr
ad_ip_parameter axi_ad9694_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9694_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9694_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9694_xcvr CONFIG.TX_OR_RX_N 0
adi_axi_jesd204_rx_create axi_ad9694_jesd 4
......
projects/grand/zu7cg/system_constr.xdc
View file @ 3428687d
# FMC_HPC 0 --> Change to board constraints GRAND
# grand
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVDS} [get_ports rx_sync_ab_p] ; ## D08 FMC_HPC0_LA01_CC_P --> SYNCINB+AB
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVDS} [get_ports rx_sync_ab_n] ; ## D09 FMC_HPC0_LA01_CC_N --> SYNCINB-AB
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVDS} [get_ports rx_sync_cd_p] ; ## not existing in AD daq3 design
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVDS} [get_ports rx_sync_cd_n] ; ## not existing in AD daq3 design
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC0_LA01_CC_P --> SYNCINB+AB
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC0_LA01_CC_N --> SYNCINB-AB
set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC0_LA05_N --> connect to SCLK_FROM_FPGA
set_property -dict {PACKAGE_PIN B26 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC0_LA09_N -->connect to CSB_FROM_FPGA
set_property -dict {PACKAGE_PIN A26 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC0_LA09_P --> connect to SDI_FROM_FPGA
......
projects/grand/zu7cg/system_top.v
View file @ 3428687d
......@@ -44,8 +44,11 @@ module system_top (
input rx_ref_clk_n,
// input rx_sysref_p,
// input rx_sysref_n,
// output rx_sync_p,
// output rx_sync_n,
output rx_sync_ab_p,
output rx_sync_ab_n,
output rx_sync_cd_p,
output rx_sync_cd_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
......@@ -115,10 +118,15 @@ module system_top (
//.IB (rx_sysref_n),
//.O (rx_sysref));
//OBUFDS i_obufds_rx_sync (
//.I (rx_sync),
//.O (rx_sync_p),
//.OB (rx_sync_n));
OBUFDS i_obufds_rx_syncAB (
.I (rx_sync),
.O (rx_sync_ab_p),
.OB (rx_sync_ab_n));
OBUFDS i_obufds_rx_syncCD (
.I (rx_sync),
.O (rx_sync_cd_p),
.OB (rx_sync_cd_n));
//IBUFDS_GTE4 i_ibufds_tx_ref_clk (
//.CEB (1'd0),
......
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