Commit 3428687d authored by Rene Habraken's avatar Rene Habraken
Browse files

cpll to qpll, added debug patches, connected syncA/B/C/D -part2

parent 911766b0
......@@ -301,10 +301,10 @@
<description>PL I2C0</description>
</component>
<component name="ddr4_sdram" display_name="DDR4 SDRAM" type="chip" sub_type="ddr" major_group="External Memory" part_name="MT40A256M16GE-075E" vendor="Micron" spec_url="https://www.micron.com/parts/dram/ddr4-sdram/mt40a256m16ge-075e">
<description>2GB DDR4 SDRAM memory SODIMM</description>
<description>4Gbit DDR4 SDRAM memory for PL</description>
<parameters>
<parameter name="ddr_type" value="ddr4"/>
<parameter name="size" value="2GB"/>
<parameter name="size" value="4Gb"/>
</parameters>
</component>
<component name="reset" display_name="FPGA Reset" type="chip" sub_type="system_reset" major_group="Reset" part_name="TL3301EP100QG" vendor="ESwitch">
......
......@@ -123,9 +123,7 @@ CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0"
#
# SD/SDIO Settings
#
CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y
CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT=y
#
# RTC Settings
......@@ -140,7 +138,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y
# boot image settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_PART_NAME="boot"
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
......@@ -149,7 +146,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
# u-boot env partition settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
......@@ -157,7 +153,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
# kernel image settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_PART_NAME="kernel"
......@@ -176,7 +171,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2"
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
......
......@@ -291,4 +291,6 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
CONFIG_USER_LAYER_2=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"
......@@ -260,7 +260,7 @@ unsigned long psu_pll_init_data(void)
* Register : IOPLL_CFG @ 0XFF5E0024
 
* PLL loop filter resistor control
* PSU_CRL_APB_IOPLL_CFG_RES 0x4
* PSU_CRL_APB_IOPLL_CFG_RES 0x2
 
* PLL charge pump control
* PSU_CRL_APB_IOPLL_CFG_CP 0x3
......@@ -275,9 +275,9 @@ unsigned long psu_pll_init_data(void)
* PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f
 
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C64U)
* (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C62U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C64U);
PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
/*##################################################################### */
 
/*
......@@ -292,16 +292,16 @@ unsigned long psu_pll_init_data(void)
* PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0
 
* The integer portion of the feedback divider to the PLL
* PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x6f
* PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x4a
 
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1
 
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00016F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00014A00U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00016F00U);
PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00014A00U);
/*##################################################################### */
 
/*
......@@ -390,14 +390,14 @@ unsigned long psu_pll_init_data(void)
* Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044
 
* Divisor value for this clock.
* PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3
* PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x2
 
* Control for a clock that will be generated in the LPD, but used in the F
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U)
* (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000200U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET,
0x00003F00U, 0x00000300U);
0x00003F00U, 0x00000200U);
/*##################################################################### */
 
/*
......@@ -874,7 +874,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc
* PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0x8
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -882,17 +882,17 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U)
* (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010800U)
*/
PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET,
0x063F3F07U, 0x06010C00U);
0x063F3F07U, 0x06010800U);
/*##################################################################### */
 
/*
* Register : GEM_TSU_REF_CTRL @ 0XFF5E0100
 
* 6 bit divider
* PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
* PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x4
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -906,10 +906,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U)
* (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010400U)
*/
PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010600U);
0x013F3F07U, 0x01010400U);
/*##################################################################### */
 
/*
......@@ -922,7 +922,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc
* PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x8
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -930,50 +930,12 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
* (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010800U)
*/
PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010C00U);
/*##################################################################### */
/*
* Register : SDIO1_REF_CTRL @ 0XFF5E0070
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8
* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U)
*/
PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010800U);
/*##################################################################### */
 
/*
* Register : SDIO_CLK_CTRL @ 0XFF18030C
* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
* [51] 1: MIO [76]
* PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0
* SoC Debug Clock Control
* (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET,
0x00020000U, 0x00000000U);
/*##################################################################### */
/*
* Register : UART0_REF_CTRL @ 0XFF5E0074
 
......@@ -984,7 +946,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xa
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -992,10 +954,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010A00U)
*/
PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
0x013F3F07U, 0x01010A00U);
/*##################################################################### */
 
/*
......@@ -1008,7 +970,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xa
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1016,10 +978,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010A00U)
*/
PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
0x013F3F07U, 0x01010A00U);
/*##################################################################### */
 
/*
......@@ -1032,7 +994,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xa
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1040,10 +1002,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010A00U)
*/
PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
0x013F3F07U, 0x01010A00U);
/*##################################################################### */
 
/*
......@@ -1056,7 +1018,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xa
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1064,10 +1026,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010A00U)
*/
PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
0x013F3F07U, 0x01010A00U);
/*##################################################################### */
 
/*
......@@ -1095,27 +1057,27 @@ unsigned long psu_clock_init_data(void)
/*##################################################################### */
 
/*
* Register : CAN1_REF_CTRL @ 0XFF5E0088
* Register : SPI1_REF_CTRL @ 0XFF5E0080
 
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1
* PSU_CRL_APB_SPI1_REF_CTRL_CLKACT 0x1
 
* 6 bit divider
* PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1
* PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0 0xf
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0
* PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0080, 0x013F3F07U ,0x01010F02U)
*/
PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
PSU_Mask_Write(CRL_APB_SPI1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F02U);
/*##################################################################### */
 
/*
......@@ -1127,7 +1089,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1
 
* 6 bit divider
* PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3
* PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x2
 
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1135,9 +1097,9 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U)
* (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000202U)
*/
PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U);
PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000202U);
/*##################################################################### */
 
/*
......@@ -1147,7 +1109,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1
 
* 6 bit divider
* PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6
* PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x4
 
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1155,10 +1117,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U)
* (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000402U)
*/
PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET,
0x01003F07U, 0x01000602U);
0x01003F07U, 0x01000402U);
/*##################################################################### */
 
/*
......@@ -1168,7 +1130,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1
 
* 6 bit divider
* PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8
* PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x5
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1176,9 +1138,9 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U)
* (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000500U)
*/
PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U);
PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000500U);
/*##################################################################### */
 
/*
......@@ -1188,7 +1150,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1
 
* 6 bit divider
* PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3
* PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x2
 
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1196,10 +1158,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U)
* (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000202U)
*/
PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET,
0x01003F07U, 0x01000302U);
0x01003F07U, 0x01000202U);
/*##################################################################### */
 
/*
......@@ -1209,7 +1171,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1
 
* 6 bit divider
* PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xa
 
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1217,10 +1179,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U)
* (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000A02U)
*/
PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET,
0x01003F07U, 0x01000F02U);
0x01003F07U, 0x01000A02U);
/*##################################################################### */
 
/*
......@@ -1230,7 +1192,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1
 
* 6 bit divider
* PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6
* PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x4
 
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1238,10 +1200,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U)
* (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000402U)
*/
PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET,
0x01003F07U, 0x01000602U);
0x01003F07U, 0x01000402U);
/*##################################################################### */
 
/*
......@@ -1251,7 +1213,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1
 
* 6 bit divider
* PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3
* PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x2
 
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1259,10 +1221,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U)
* (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000202U)
*/
PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET,
0x01003F07U, 0x01000302U);
0x01003F07U, 0x01000202U);
/*##################################################################### */
 
/*
......@@ -1275,7 +1237,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xa
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1283,10 +1245,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)
* (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010A00U)
*/
PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
0x013F3F07U, 0x01010A00U);
/*##################################################################### */
 
/*
......@@ -1299,7 +1261,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0x6
* PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0x4
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1307,10 +1269,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01010600U)
* (OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01010400U)
*/
PSU_Mask_Write(CRL_APB_PL1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010600U);
0x013F3F07U, 0x01010400U);
/*##################################################################### */
 
/*
......@@ -1323,7 +1285,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x3
* PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x2
 
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1331,10 +1293,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_PL2_REF_CTRL_SRCSEL 0x0
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010300U)
* (OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010200U)
*/
PSU_Mask_Write(CRL_APB_PL2_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010300U);
0x013F3F07U, 0x01010200U);
/*##################################################################### */
 
/*
......@@ -1344,7 +1306,7 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1
 
* 6 bit divider
* PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e
* PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x14
 
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
......@@ -1355,10 +1317,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U)
* (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011402U)
*/
PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET,
0x013F3F07U, 0x01011E02U);
0x013F3F07U, 0x01011402U);
/*##################################################################### */
 
/*
......@@ -1380,7 +1342,7 @@ unsigned long psu_clock_init_data(void)
* Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128
 
* 6 bit divider
* PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf
* PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xa
 
* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
* only be toggled after 4 cycles of the old clock and 4 cycles of the new
......@@ -1391,10 +1353,10 @@ unsigned long psu_clock_init_data(void)
* PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1
 
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U)
* (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000A00U)
*/
PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET,
0x01003F07U, 0x01000F00U);
0x01003F07U, 0x01000A00U);
/*##################################################################### */
 
/*
......@@ -3453,7 +3415,7 @@ unsigned long psu_ddr_init_data(void)
* : 5 The selected HIF address bit is determined by adding the internal ba
* se to the value of this field. If set to 15, this column address bit is
* set to 0.
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x1
 
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 4. - Half bus width mode: Selects the HIF address bit used as colu
......@@ -3462,7 +3424,7 @@ unsigned long psu_ddr_init_data(void)
* 4 The selected HIF address bit is determined by adding the internal bas
* e to the value of this field. If set to 15, this column address bit is s
* et to 0.
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x1
 
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 3. - Half bus width mode: Selects the HIF address bit used as colu
......@@ -3472,7 +3434,7 @@ unsigned long psu_ddr_init_data(void)
* value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1
* 6, it is required to program this to 0, hence register does not exist in
* this case.
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x1
 
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 2. - Half bus width mode: Selects the HIF address bit used as colu
......@@ -3481,12 +3443,12 @@ unsigned long psu_ddr_init_data(void)
* elected HIF address bit is determined by adding the internal base to the
* value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
* or 16, it is required to program this to 0.
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x1
 
* Address Map Register 2
* (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U)
* (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x01010101U)
*/
PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U);
PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x01010101U);
/*##################################################################### */
 
/*
......@@ -3516,7 +3478,7 @@ unsigned long psu_ddr_init_data(void)
* and hence no source address bit can be mapped to column address bit 10.
* In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA