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Commit 4705d96e authored by Rene Habraken's avatar Rene Habraken
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debugging driver, all info clk in DT

parent d8f4ff79
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meta-adi/meta-adi-xilinx/recipes-bsp/device-tree/files/zynqmp-zu7cg-rev1-ad9694.dts
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......@@ -203,7 +203,67 @@
#size-cells = <0>;
clocks = <&xtal48MHz>;
clock-names = "xtal";
clock-output-names = "out0", "out1", "out2", "out3";
silabs,pll-m-num = <13600>; /* PLL at 13.6 GHz */
silabs,pll-m-den = <48>;
silabs,reprogram; /* Reprogram to allow AD driver setting the lane rate */
assigned-clocks = <&si5340 1 0>,
<&si5340 1 1>,
<&si5340 1 2>,
<&si5340 1 3>,
<&si5340 0 0>,
<&si5340 0 1>,
<&si5340 0 2>,
<&si5340 0 3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&si5340 1 0>,
<&si5340 1 0>,
<&si5340 1 0>,
<&si5340 1 0>;
assigned-clock-rates = <400000000>, /* wat betekent dit en waar komt deze waarde vandaan? 0 */
<0>,
<0>,
<0>,
<27000000>, /* out 0 */
<300000000>,
<31250000>, /*3.125 MHz */
<1000000000>;
out@0 {
/* PS_REF_CLK (27MHz) */
reg = <0>;
silabs,format = <4>; /* LVCMOS*/
silabs,common-mode = <3>;
silabs,amplitude = <3>;
always-on; /* assigned-clocks does not enable, so do it here */
};
out@1 {
/* PL_DDR_CLK (300MHz) */
reg = <1>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
always-on;
};
out@2 {
/* MGTREFCLK0 RX refclk (???MHz) */
reg = <2>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
always-on;
};
out@3 {
/* ADC_REF_CLK (1000MHz) */
reg = <3>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
always-on;
};
};
/* MAXIM_PMBUS - 00 */
......
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