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Commit 4941640a authored by Rene Habraken's avatar Rene Habraken
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cpack2, dma128

parent d9f72980
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library/axi_ad9694/axi_ad9694.v
View file @ 4941640a
......@@ -96,7 +96,7 @@ module axi_ad9694 #(
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_LANES (4),
.NUM_CHANNELS (2),
.NUM_CHANNELS (4),
.SAMPLES_PER_FRAME (1),
.CONVERTER_RESOLUTION (14),
.BITS_PER_SAMPLE (16),
......
meta-adi/grand_zcu7/project-spec/configs/config
View file @ 4941640a
......@@ -290,4 +290,7 @@ CONFIG_USER_LAYER_2=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"
meta-adi/grand_zcu7/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend
View file @ 4941640a
......@@ -4,7 +4,6 @@ SRC_URI += "file://user_2020-07-07-12-40-00.cfg \
SRC_URI_append += " \
file://0001-debug-txcvr.patch \
file://0001-debug-ad9680.patch \
"
FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
......
meta-adi/meta-adi-xilinx/recipes-bsp/device-tree/files/zynqmp-zu7cg-rev1-ad9694.dts
View file @ 4941640a
......@@ -228,7 +228,7 @@
<0>,
<27000000>, /* out 0 */
<300000000>,
<500000000>, /*500 MHz */
<250000000>, /*500 MHz */
<1000000000>;
out@1 {
......@@ -241,7 +241,7 @@
};
out@2 {
/* MGTREFCLK0 RX refclk (500MHz) */
/* MGTREFCLK0 RX refclk (250MHz) */
reg = <2>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
......
projects/common/zu7cg/zu7cg_system_constr.xdc
View file @ 4941640a
......@@ -2,29 +2,30 @@
# constraints
# gpio (switches, leds and such)
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[0]}]
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[1]}]
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[2]}]
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[3]}]
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[4]}]
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[5]}]
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[6]}]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[7]}]
#set_property -dict {PACKAGE_PIN AE14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_E --> n.c.
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_S
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[9]}]
#set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_N --> n.c.
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[11]}]
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_i[12]}]
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_o[0]}]
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_o[1]}]
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_o[2]}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_o[3]}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_o[4]}]
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_o[5]}]
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_o[6]}]
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {gpio_bd_o[7]}]
# Define SPI clock
create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO]
create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO]
create_clock -period 40.000 -name spi0_clk [get_pins -hier */EMIOSPI0SCLKO]
create_clock -period 40.000 -name spi1_clk [get_pins -hier */EMIOSPI1SCLKO]
projects/grand/common/grand_bd.tcl
View file @ 4941640a
......@@ -3,7 +3,7 @@ source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_fifo_name axi_ad9694_fifo
set adc_data_width 128
set adc_dma_data_width 64
set adc_dma_data_width 128
#set dac_fifo_name axi_ad9152_fifo
#set dac_data_width 128
......@@ -67,8 +67,8 @@ ad_ip_parameter axi_ad9694_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad9694_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9694_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9694_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9694_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9694_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_parameter axi_ad9694_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad9694_dma CONFIG.DMA_DATA_WIDTH_DEST 128
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
......
projects/grand/zu7cg/system_constr.xdc
View file @ 4941640a
# FMC_HPC 0 --> Change to board constraints GRAND
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVDS} [get_ports rx_sync_ab_p] ; ## D08 FMC_HPC0_LA01_CC_P --> SYNCINB+AB
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVDS} [get_ports rx_sync_ab_n] ; ## D09 FMC_HPC0_LA01_CC_N --> SYNCINB-AB
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVDS} [get_ports rx_sync_cd_p] ; ## not existing in AD daq3 design
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVDS} [get_ports rx_sync_cd_n] ; ## not existing in AD daq3 design
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVDS} [get_ports rx_sync_ab_p]
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVDS} [get_ports rx_sync_ab_n]
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVDS} [get_ports rx_sync_cd_p]
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVDS} [get_ports rx_sync_cd_n]
set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC0_LA05_N --> connect to SCLK_FROM_FPGA
set_property -dict {PACKAGE_PIN B26 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC0_LA09_N -->connect to CSB_FROM_FPGA
set_property -dict {PACKAGE_PIN A26 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC0_LA09_P --> connect to SDI_FROM_FPGA
set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## C11 FMC_HPC0_LA06_N --> connect to open pin
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC0_LA06_P --> connect to PWDN_TO_FPGA
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18} [get_ports adc_pd]
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC0_LA11_P --> connect to FDA_TO_FPGA
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC0_LA11_N --> connect to FDB_TO_FPGA
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports adc_fda]
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports adc_fdb]
# clocks
#create_clock -name tx_ref_clk -period 1.0 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 1.0 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 2.0 [get_pins i_system_wrapper/system_i/util_grand_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
create_clock -period 1.000 -name rx_ref_clk [get_ports rx_ref_clk_p]
create_clock -period 2.000 -name rx_div_clk [get_pins i_system_wrapper/system_i/util_grand_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
# pin assignments below are for reference only and are ignored by the tool!
set_property -dict {PACKAGE_PIN L8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_P
set_property -dict {PACKAGE_PIN L7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC0_GBTCLK1_M2C_C_N
set_property -dict {PACKAGE_PIN L8} [get_ports rx_ref_clk_p]
set_property -dict {PACKAGE_PIN L7} [get_ports rx_ref_clk_n]
#set_property -dict {PACKAGE_PIN G8 } [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P
#set_property -dict {PACKAGE_PIN G7 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC0_GBTCLK0_M2C_C_N
set_property -dict {PACKAGE_PIN N4 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC0_DP3_M2C_P
set_property -dict {PACKAGE_PIN N3 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC0_DP3_M2C_N
set_property -dict {PACKAGE_PIN M2 } [get_ports rx_data_p[1]] ; ## C06 FMC_HPC0_DP0_M2C_P
set_property -dict {PACKAGE_PIN M1 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC0_DP0_M2C_N
set_property -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC0_DP2_M2C_P
set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC0_DP2_M2C_N
set_property -dict {PACKAGE_PIN N4} [get_ports {rx_data_p[0]}]
set_property -dict {PACKAGE_PIN N3} [get_ports {rx_data_n[0]}]
set_property -dict {PACKAGE_PIN M2} [get_ports {rx_data_p[1]}]
set_property -dict {PACKAGE_PIN M1} [get_ports {rx_data_n[1]}]
set_property -dict {PACKAGE_PIN K2} [get_ports {rx_data_p[2]}]
set_property -dict {PACKAGE_PIN K1} [get_ports {rx_data_n[2]}]
set_property -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC0_DP1_M2C_P
set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC0_DP1_M2C_N
......@@ -83,5 +83,6 @@ set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3]]
#create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
# remove when ila's are removed from firmware
set_max_delay -from [get_clocks rx_div_clk] -to [get_clocks clk_pl_0] 2.0
set_max_delay -from [get_clocks rx_div_clk] -to [get_clocks clk_pl_0] 2.000
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