Commit 52f5ce76 authored by Rene Habraken's avatar Rene Habraken
Browse files

revert old settings (from TOPIC) of clock node device tree

parent 0b730d96
......@@ -290,7 +290,7 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
#
# User Layers
#
CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/meta-adi/meta-adi-core"
CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/meta-adi/meta-adi-xilinx"
CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
CONFIG_USER_LAYER_2=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=mtd:jffs2 rw rootfstype=jffs2"
......@@ -2,8 +2,7 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI += " \
file://0001-fix-the-clock-frequency-generation.patch \
file://pl-delete-nodes-zynqmp-zcu102-rev10-fmcdaq3.dtsi \
file://adi-daq3_v2.dtsi"
file://pl-delete-nodes-zynqmp-zcu102-rev10-fmcdaq3.dtsi"
# Set this variable with the desired device tree
KERNEL_DTB = "file://zynqmp-zu7cg-rev1-ad9694.dts"
......@@ -52,7 +51,7 @@ set_common_vars() {
# Add the /include "pl-delete-nodes-*" to remove all the duplicated labels between ADI device trees and pl.dtsi (generated by petalinux).
do_configure_append() {
cp "/home/rene/Data/FPGA_workdir/adi/meta-adi/meta-adi-xilinx/recipes-bsp/device-tree/files/zynqmp-zu7cg-rev1-ad9694.dts" ${WORKDIR}/analog-devices.dtsi
cp "/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx/recipes-bsp/device-tree/files/zynqmp-zu7cg-rev1-ad9694.dts" ${WORKDIR}/analog-devices.dtsi
[ ! -e "${WORKDIR}/pl-delete-nodes-zynqmp-zcu102-rev10-fmcdaq3.dtsi" ] && \
{ bbfatal "Error: Could not find "pl-delete-nodes-zynqmp-zcu102-rev10-fmcdaq3.dtsi" in \"${WORKDIR}\""; }
......
......@@ -194,6 +194,78 @@
reg = <0x54>;
};
/* Programmable clock */
si5340: si5340@76 {
reg = <0x76>;
compatible = "silabs,si5340";
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&xtal48MHz>;
clock-names = "xtal";
assigned-clocks = <&si5340 1 0>,
<&si5340 1 1>,
<&si5340 1 2>,
<&si5340 1 3>,
<&si5340 0 0>,
<&si5340 0 1>,
<&si5340 0 2>,
<&si5340 0 3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&si5340 1 0>,
<&si5340 1 1>,
<&si5340 1 2>,
<&si5340 1 3>;
assigned-clock-rates = <0>, /* synth 0 */
<0>,
<0>,
<0>,
<27000000>, /* out 0 */
<300000000>,
<500000000>,
<1000000000>;
out@0 {
/* PS_REF_CLK (27MHz) */
reg = <0>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
silabs,synth-master;
always-on; /* assigned-clocks does not enable, so do it here */
};
out@1 {
/* PL_DDR_CLK (300MHz) */
reg = <1>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
silabs,synth-master;
always-on;
};
out@2 {
/* MGTREFCLK0 RX refclk (500MHz) */
reg = <2>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
silabs,synth-master;
always-on;
};
out@3 {
/* ADC_REF_CLK (1000MHz) */
reg = <3>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
silabs,synth-master;
always-on;
};
};
/* MAXIM_PMBUS - 00 */
u88: max15301@0A { /* u88 */
compatible = "maxim,max15301";
......@@ -227,7 +299,7 @@
compatible = "maxim,max15303";
reg = <0x17>;
};
u68: max15301@1a { /* u68 */
u68: max15301@1a { /* u68 */
compatible = "maxim,max15301";
reg = <0x1a>;
};
......@@ -235,7 +307,7 @@
compatible = "maxim,max15303";
reg = <0x1d>;
};
u52: max20751@72 { /* u52 */
u52: max20751@72 { /* u52 */
compatible = "maxim,max20751";
reg = <0x72>;
};
......
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