Commit 647d6c85 authored by Rene Habraken's avatar Rene Habraken
Browse files

modified port width ADC core

parent c11d43bc
......@@ -57,16 +57,16 @@ module axi_ad9694 #(
output adc_clk,
output adc_enable_0,
output adc_valid_0,
output [32:0] adc_data_0,
output [31:0] adc_data_0,
output adc_enable_1,
output adc_valid_1,
output [32:0] adc_data_1,
output [31:0] adc_data_1,
output adc_enable_2,
output adc_valid_2,
output [32:0] adc_data_2,
output [31:0] adc_data_2,
output adc_enable_3,
output adc_valid_3,
output [32:0] adc_data_3,
output [31:0] adc_data_3,
input adc_dovf,
// axi interface
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment