Commit aa12edbb authored by Rene Habraken's avatar Rene Habraken
Browse files

removed sysref from DT and enabled correct SPI bus in HW

parent 3428687d
......@@ -123,9 +123,7 @@ CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0"
#
# SD/SDIO Settings
#
CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y
CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT=y
#
# RTC Settings
......@@ -140,7 +138,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y
# boot image settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_PART_NAME="boot"
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
......@@ -149,7 +146,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
# u-boot env partition settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
......@@ -157,7 +153,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
# kernel image settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_PART_NAME="kernel"
......@@ -176,7 +171,6 @@ CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2"
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
......@@ -291,6 +285,4 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
CONFIG_USER_LAYER_2=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"
......@@ -1056,30 +1056,6 @@ unsigned long psu_clock_init_data(void)
0x013F3F07U, 0x01010F02U);
/*##################################################################### */
 
/*
* Register : SPI1_REF_CTRL @ 0XFF5E0080
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_SPI1_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0 0xf
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0080, 0x013F3F07U ,0x01010F02U)
*/
PSU_Mask_Write(CRL_APB_SPI1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F02U);
/*##################################################################### */
/*
* Register : CPU_R5_CTRL @ 0XFF5E0090
 
......@@ -12856,6 +12832,194 @@ unsigned long psu_mio_init_data(void)
PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000000U);
/*##################################################################### */
 
/*
* Register : MIO_PIN_52 @ 0XFF1800D0
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
* clk- (TX RGMII clock)
* PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i
* n- (ULPI Clock)
* PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy
* _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
* 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
* TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
* lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out
* put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
* lk- (Trace Port Clock)
* PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 4
* Configures MIO Pin 52 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000080U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000080U);
/*##################################################################### */
/*
* Register : MIO_PIN_53 @ 0XFF1800D4
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
* [0]- (TX RGMII data)
* PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir-
* (Data bus direction control)
* PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_
* rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
* , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
* TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou
* tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
* receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
* Signal)
* PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 4
* Configures MIO Pin 53 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000080U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000080U);
/*##################################################################### */
/*
* Register : MIO_PIN_54 @ 0XFF1800D8
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
* [1]- (TX RGMII data)
* PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data
* bus)
* PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_
* rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
* , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
* TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I
* nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
* rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 4
* Configures MIO Pin 54 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000080U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000080U);
/*##################################################################### */
/*
* Register : MIO_PIN_55 @ 0XFF1800DC
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
* [2]- (TX RGMII data)
* PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt-
* (Data flow control signal from the PHY)
* PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy
* _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
* 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
* TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
* , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out-
* (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
* output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 4
* Configures MIO Pin 55 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000080U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000080U);
/*##################################################################### */
/*
* Register : MIO_PIN_56 @ 0XFF1800E0
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
* [3]- (TX RGMII data)
* PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data
* bus)
* PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy
* _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
* 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
* tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
* 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc
* k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
* utput, tracedq[2]- (Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 4
* Configures MIO Pin 56 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000080U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000080U);
/*##################################################################### */
/*
* Register : MIO_PIN_57 @ 0XFF1800E4
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
* ctl- (TX RGMII control)
* PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data
* bus)
* PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_
* rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
* , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
* atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
* spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC
* Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
* trace, Output, tracedq[3]- (Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 4
* Configures MIO Pin 57 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000080U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000080U);
/*##################################################################### */
/*
* Register : MIO_PIN_64 @ 0XFF180100
 
......@@ -13473,11 +13637,29 @@ unsigned long psu_mio_init_data(void)
* Master Tri-state Enable for pin 51, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0
 
* Master Tri-state Enable for pin 52, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 0
* Master Tri-state Enable for pin 53, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 0
* Master Tri-state Enable for pin 54, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0
* Master Tri-state Enable for pin 55, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 0
* Master Tri-state Enable for pin 56, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0
* Master Tri-state Enable for pin 57, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0
* MIO pin Tri-state Enables, 63:32
* (OFFSET, MASK, VALUE) (0XFF180208, 0x000FFFFFU ,0x00000000U)
* (OFFSET, MASK, VALUE) (0XFF180208, 0x03FFFFFFU ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET,
0x000FFFFFU, 0x00000000U);
0x03FFFFFFU, 0x00000000U);
/*##################################################################### */
 
/*
......@@ -15387,15 +15569,12 @@ unsigned long psu_peripherals_init_data(void)
* Block level reset
* PSU_CRL_APB_RST_LPD_IOU2_SPI0_RESET 0
 
* Block level reset
* PSU_CRL_APB_RST_LPD_IOU2_SPI1_RESET 0
* Software control register for the IOU block. Each bit will cause a singl
* erperipheral or part of the peripheral to be reset.
* (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000018U ,0x00000000U)
* (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000008U ,0x00000000U)
*/
PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
0x00000018U, 0x00000000U);
0x00000008U, 0x00000000U);
/*##################################################################### */
 
/*
......
......@@ -925,8 +925,6 @@
#define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124
#undef CRL_APB_SPI0_REF_CTRL_OFFSET
#define CRL_APB_SPI0_REF_CTRL_OFFSET 0XFF5E007C
#undef CRL_APB_SPI1_REF_CTRL_OFFSET
#define CRL_APB_SPI1_REF_CTRL_OFFSET 0XFF5E0080
#undef CRL_APB_CPU_R5_CTRL_OFFSET
#define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090
#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
......@@ -1324,48 +1322,6 @@
#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 0x00000007U
 
/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
#undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK
#define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 0x01001800
#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 0x01000000U
/*
* 6 bit divider
*/
#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL
#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK
#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
/*
* 6 bit divider
*/
#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL
#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK
#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
*/
#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL
#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK
#define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 0x00000007U
/*
* Turing this off will shut down the OCM, some parts of the APM, and preve
* nt transactions going from the FPD to the LPD and could lead to system h
......@@ -23322,6 +23278,18 @@
#define IOU_SLCR_MIO_PIN_50_OFFSET 0XFF1800C8
#undef IOU_SLCR_MIO_PIN_51_OFFSET
#define IOU_SLCR_MIO_PIN_51_OFFSET 0XFF1800CC
#undef IOU_SLCR_MIO_PIN_52_OFFSET
#define IOU_SLCR_MIO_PIN_52_OFFSET 0XFF1800D0
#undef IOU_SLCR_MIO_PIN_53_OFFSET
#define IOU_SLCR_MIO_PIN_53_OFFSET 0XFF1800D4
#undef IOU_SLCR_MIO_PIN_54_OFFSET
#define IOU_SLCR_MIO_PIN_54_OFFSET 0XFF1800D8
#undef IOU_SLCR_MIO_PIN_55_OFFSET
#define IOU_SLCR_MIO_PIN_55_OFFSET 0XFF1800DC
#undef IOU_SLCR_MIO_PIN_56_OFFSET
#define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0
#undef IOU_SLCR_MIO_PIN_57_OFFSET
#define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4
#undef IOU_SLCR_MIO_PIN_64_OFFSET
#define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100
#undef IOU_SLCR_MIO_PIN_65_OFFSET
......@@ -25829,6 +25797,308 @@
#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U
 
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
* clk- (TX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U
/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i
* n- (ULPI Clock)
*/
#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK
#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2
#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U
/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
*/
#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK
#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3
#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U
/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy
* _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
* 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
* TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
* lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out
* put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
* lk- (Trace Port Clock)
*/
#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK
#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
* [0]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U
/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir-
* (Data bus direction control)
*/
#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK
#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2
#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U
/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
*/
#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK
#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3
#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U
/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_
* rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
* , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
* TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou
* tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
* receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
* Signal)
*/
#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK
#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
* [1]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U
/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data
* bus)
*/
#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK
#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2
#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U
/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
*/
#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK
#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3
#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U
/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_
* rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
* , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
* TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I
* nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
* rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK
#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
* [2]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U
/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt-
* (Data flow control signal from the PHY)
*/
#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK
#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2
#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U
/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
*/
#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK
#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3
#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U
/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy
* _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
* 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
* TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
* , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out-
* (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
* output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK
#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
* [3]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U
/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data