Commit bc2279f5 authored by Rene Habraken's avatar Rene Habraken
Browse files

changed refclk and reset to qpll

parent aa12edbb
# create board design
# default ports
# default ports RH: replaced by board file presets /opt/Xilinx/vivado/data/board
create_bd_port -dir O -from 2 -to 0 spi0_csn
create_bd_port -dir O spi0_sclk
create_bd_port -dir O spi0_mosi
create_bd_port -dir I spi0_miso
#create_bd_port -dir O -from 2 -to 0 spi0_csn
#create_bd_port -dir O spi0_sclk
#create_bd_port -dir O spi0_mosi
#create_bd_port -dir I spi0_miso
create_bd_port -dir O -from 2 -to 0 spi1_csn
create_bd_port -dir O spi1_sclk
create_bd_port -dir O spi1_mosi
create_bd_port -dir I spi1_miso
#create_bd_port -dir O -from 2 -to 0 spi1_csn
#create_bd_port -dir O spi1_sclk
#create_bd_port -dir O spi1_mosi
#create_bd_port -dir I spi1_miso
create_bd_port -dir I -from 94 -to 0 gpio_i
create_bd_port -dir O -from 94 -to 0 gpio_o
......@@ -39,18 +39,18 @@ ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
set_property -dict [list \
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1 \
CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1 \
CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1 \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100 \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE 1 \
CONFIG.PSU__SPI1__PERIPHERAL__IO EMIO \
CONFIG.PSU__SPI1__GRP_SS1__ENABLE 1 \
CONFIG.PSU__SPI1__GRP_SS2__ENABLE 1 \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ 100 \
] [get_bd_cells sys_ps8]
#set_property -dict [list \
# CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1 \
# CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
# CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1 \
# CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1 \
# CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100 \
# CONFIG.PSU__SPI1__PERIPHERAL__ENABLE 1 \
# CONFIG.PSU__SPI1__PERIPHERAL__IO EMIO \
# CONFIG.PSU__SPI1__GRP_SS1__ENABLE 1 \
# CONFIG.PSU__SPI1__GRP_SS2__ENABLE 1 \
# CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ 100 \
#] [get_bd_cells sys_ps8]
# processor system reset instances for all the three system clocks
......@@ -100,33 +100,33 @@ ad_connect gpio_i sys_ps8/emio_gpio_i
ad_connect gpio_o sys_ps8/emio_gpio_o
ad_connect gpio_t sys_ps8/emio_gpio_t
# spi
ad_ip_instance xlconcat spi0_csn_concat
ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
ad_connect spi0_csn_concat/dout spi0_csn
ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
ad_connect sys_ps8/emio_spi0_m_i spi0_miso
ad_connect sys_ps8/emio_spi0_ss_i_n VCC
ad_connect sys_ps8/emio_spi0_sclk_i GND
ad_connect sys_ps8/emio_spi0_s_i GND
ad_ip_instance xlconcat spi1_csn_concat
ad_ip_parameter spi1_csn_concat CONFIG.NUM_PORTS 3
ad_connect sys_ps8/emio_spi1_ss_o_n spi1_csn_concat/In0
ad_connect sys_ps8/emio_spi1_ss1_o_n spi1_csn_concat/In1
ad_connect sys_ps8/emio_spi1_ss2_o_n spi1_csn_concat/In2
ad_connect spi1_csn_concat/dout spi1_csn
ad_connect sys_ps8/emio_spi1_sclk_o spi1_sclk
ad_connect sys_ps8/emio_spi1_m_o spi1_mosi
ad_connect sys_ps8/emio_spi1_m_i spi1_miso
ad_connect sys_ps8/emio_spi1_ss_i_n VCC
ad_connect sys_ps8/emio_spi1_sclk_i GND
ad_connect sys_ps8/emio_spi1_s_i GND
# spi RH: mio pins are used in GRAND setup
#ad_ip_instance xlconcat spi0_csn_concat
#ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
#ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
#ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
#ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
#ad_connect spi0_csn_concat/dout spi0_csn
#ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
#ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
#ad_connect sys_ps8/emio_spi0_m_i spi0_miso
#ad_connect sys_ps8/emio_spi0_ss_i_n VCC
#ad_connect sys_ps8/emio_spi0_sclk_i GND
#ad_connect sys_ps8/emio_spi0_s_i GND
#ad_ip_instance xlconcat spi1_csn_concat
#ad_ip_parameter spi1_csn_concat CONFIG.NUM_PORTS 3
#ad_connect sys_ps8/emio_spi1_ss_o_n spi1_csn_concat/In0
#ad_connect sys_ps8/emio_spi1_ss1_o_n spi1_csn_concat/In1
#ad_connect sys_ps8/emio_spi1_ss2_o_n spi1_csn_concat/In2
#ad_connect spi1_csn_concat/dout spi1_csn
#ad_connect sys_ps8/emio_spi1_sclk_o spi1_sclk
#ad_connect sys_ps8/emio_spi1_m_o spi1_mosi
#ad_connect sys_ps8/emio_spi1_m_i spi1_miso
#ad_connect sys_ps8/emio_spi1_ss_i_n VCC
#ad_connect sys_ps8/emio_spi1_sclk_i GND
#ad_connect sys_ps8/emio_spi1_s_i GND
# system id
......
......@@ -79,11 +79,11 @@ if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_ip_instance util_adxcvr util_grand_xcvr
ad_ip_parameter util_grand_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_grand_xcvr CONFIG.TX_NUM_OF_LANES 0
#ad_ip_parameter util_grand_xcvr CONFIG.QPLL_REFCLK_DIV 1
#ad_ip_parameter util_grand_xcvr CONFIG.QPLL_FBDIV_RATIO 1
#ad_ip_parameter util_grand_xcvr CONFIG.QPLL_FBDIV 0x30; # 20
ad_ip_parameter util_grand_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_grand_xcvr CONFIG.QPLL_FBDIV_RATIO 1
ad_ip_parameter util_grand_xcvr CONFIG.QPLL_FBDIV 0x30; # 20
ad_ip_parameter util_grand_xcvr CONFIG.RX_OUT_DIV 1
#ad_ip_parameter util_grand_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_grand_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_grand_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
ad_ip_parameter util_grand_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020
......@@ -96,9 +96,9 @@ create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
#Prevent error on util_grand_xcvr for missing clock input.
ad_xcvrpll rx_ref_clk_0 util_grand_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_grand_xcvr/cpll_ref_clk_*
#ad_xcvrpll axi_ad9152_xcvr/up_pll_rst util_daq3_xcvr/up_qpll_rst_*
ad_xcvrpll rx_ref_clk_0 util_grand_xcvr/qpll_ref_clk_*
ad_xcvrpll axi_ad9694_xcvr/up_pll_rst util_grand_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9694_xcvr/up_pll_rst util_grand_xcvr/up_cpll_rst_*
# connections (dac)
......
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