Commit bf05213d authored by Rene Habraken's avatar Rene Habraken
Browse files

Merge remote-tracking branch 'origin/changefrm2to4converters'

parents a2c6fcda ff43fe37
...@@ -57,10 +57,16 @@ module axi_ad9694 #( ...@@ -57,10 +57,16 @@ module axi_ad9694 #(
output adc_clk, output adc_clk,
output adc_enable_0, output adc_enable_0,
output adc_valid_0, output adc_valid_0,
output [63:0] adc_data_0, output [31:0] adc_data_0,
output adc_enable_1, output adc_enable_1,
output adc_valid_1, output adc_valid_1,
output [63:0] adc_data_1, output [31:0] adc_data_1,
output adc_enable_2,
output adc_valid_2,
output [31:0] adc_data_2,
output adc_enable_3,
output adc_valid_3,
output [31:0] adc_data_3,
input adc_dovf, input adc_dovf,
// axi interface // axi interface
...@@ -96,7 +102,7 @@ module axi_ad9694 #( ...@@ -96,7 +102,7 @@ module axi_ad9694 #(
.SPEED_GRADE (SPEED_GRADE), .SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE), .DEV_PACKAGE (DEV_PACKAGE),
.NUM_LANES (4), .NUM_LANES (4),
.NUM_CHANNELS (2), .NUM_CHANNELS (4),
.SAMPLES_PER_FRAME (1), .SAMPLES_PER_FRAME (1),
.CONVERTER_RESOLUTION (14), .CONVERTER_RESOLUTION (14),
.BITS_PER_SAMPLE (16), .BITS_PER_SAMPLE (16),
...@@ -110,9 +116,9 @@ module axi_ad9694 #( ...@@ -110,9 +116,9 @@ module axi_ad9694 #(
.link_data (rx_data), .link_data (rx_data),
.link_ready (rx_ready), .link_ready (rx_ready),
.enable ({adc_enable_1,adc_enable_0}), .enable ({adc_enable_3,adc_enable_2,adc_enable_1,adc_enable_0}),
.adc_valid ({adc_valid_1,adc_valid_0}), .adc_valid ({adc_valid_3,adc_valid_2,adc_valid_1,adc_valid_0}),
.adc_data ({adc_data_1,adc_data_0}), .adc_data ({adc_data_3,adc_data_2,adc_data_1,adc_data_0}),
.adc_dovf (adc_dovf), .adc_dovf (adc_dovf),
.s_axi_aclk (s_axi_aclk), .s_axi_aclk (s_axi_aclk),
......
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
DEV_PACKAGE \
SPEED_GRADE \
FPGA_FAMILY \
FPGA_TECHNOLOGY"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
...@@ -223,12 +223,17 @@ CONFIG_SUBSYSTEM_U__BOOT_TFTPSERVER_IP="AUTO" ...@@ -223,12 +223,17 @@ CONFIG_SUBSYSTEM_U__BOOT_TFTPSERVER_IP="AUTO"
# #
# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set # CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set # CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set
# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set CONFIG_SUBSYSTEM_ROOTFS_JFFS2=y
CONFIG_SUBSYSTEM_ROOTFS_NFS=y # CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
# CONFIG_SUBSYSTEM_ROOTFS_SD is not set # CONFIG_SUBSYSTEM_ROOTFS_SD is not set
# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set # CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
CONFIG_SUBSYSTEM_NFSROOT_DIR="/srv/nfs" # CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_8 is not set
CONFIG_SUBSYSTEM_NFSSERVER_IP="192.168.10.1" # CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_16 is not set
# CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_32 is not set
# CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_64 is not set
CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_128=y
# CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_256 is not set
# CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_512 is not set
CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub" CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000 CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y
...@@ -285,10 +290,4 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r ...@@ -285,10 +290,4 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core" CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx" CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
CONFIG_USER_LAYER_2="" CONFIG_USER_LAYER_2=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=mtd:jffs2 rw rootfstype=jffs2"
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"
...@@ -223,12 +223,17 @@ CONFIG_SUBSYSTEM_U__BOOT_TFTPSERVER_IP="AUTO" ...@@ -223,12 +223,17 @@ CONFIG_SUBSYSTEM_U__BOOT_TFTPSERVER_IP="AUTO"
# #
# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set # CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set # CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set
# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set CONFIG_SUBSYSTEM_ROOTFS_JFFS2=y
CONFIG_SUBSYSTEM_ROOTFS_NFS=y # CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
# CONFIG_SUBSYSTEM_ROOTFS_SD is not set # CONFIG_SUBSYSTEM_ROOTFS_SD is not set
# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set # CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
CONFIG_SUBSYSTEM_NFSROOT_DIR="/srv/nfs" # CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_8 is not set
CONFIG_SUBSYSTEM_NFSSERVER_IP="192.168.10.1" # CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_16 is not set
# CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_32 is not set
# CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_64 is not set
CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_128=y
# CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_256 is not set
# CONFIG_SUBSYSTEM_JFFS2_ERASE_SIZE_512 is not set
CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub" CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000 CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y
...@@ -285,4 +290,4 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r ...@@ -285,4 +290,4 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core" CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx" CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
CONFIG_USER_LAYER_2="" CONFIG_USER_LAYER_2=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw" CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=mtd:jffs2 rw rootfstype=jffs2"
...@@ -13020,6 +13020,196 @@ unsigned long psu_mio_init_data(void) ...@@ -13020,6 +13020,196 @@ unsigned long psu_mio_init_data(void)
PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000080U); PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000080U);
/*##################################################################### */ /*##################################################################### */
   
/*
* Register : MIO_PIN_58 @ 0XFF1800E8
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
* lk- (RX RGMII clock)
* PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp-
* (Asserted to end or interrupt transfers)
* PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_
* rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
* , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
* TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl
* k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
* t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
* Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0
* Configures MIO Pin 58 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000000U);
/*##################################################################### */
/*
* Register : MIO_PIN_59 @ 0XFF1800EC
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
* 0]- (RX RGMII data)
* PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data
* bus)
* PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy
* _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
* 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
* TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
* utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
* T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
* atabus)
* PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0
* Configures MIO Pin 59 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000000U);
/*##################################################################### */
/*
* Register : MIO_PIN_60 @ 0XFF1800F0
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
* 1]- (RX RGMII data)
* PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data
* bus)
* PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy
* _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
* 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
* G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
* Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
* er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0
* Configures MIO Pin 60 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000000U);
/*##################################################################### */
/*
* Register : MIO_PIN_61 @ 0XFF1800F4
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
* 2]- (RX RGMII data)
* PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data
* bus)
* PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_
* rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
* , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
* TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output,
* spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
* (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
* ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0
* Configures MIO Pin 61 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000000U);
/*##################################################################### */
/*
* Register : MIO_PIN_62 @ 0XFF1800F8
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
* 3]- (RX RGMII data)
* PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data
* bus)
* PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0=
* gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph
* y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
* c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
* atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
* i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo
* ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
* t, tracedq[8]- (Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0
* Configures MIO Pin 62 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000000U);
/*##################################################################### */
/*
* Register : MIO_PIN_63 @ 0XFF1800FC
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
* tl- (RX RGMII control )
* PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data
* bus)
* PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 0
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
* PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0=
* gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p
* hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
* 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
* (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
* 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
* TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
* tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
* PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0
* Configures MIO Pin 63 peripheral interface mapping
* (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000000U);
/*##################################################################### */
/* /*
* Register : MIO_PIN_64 @ 0XFF180100 * Register : MIO_PIN_64 @ 0XFF180100
   
...@@ -13655,11 +13845,29 @@ unsigned long psu_mio_init_data(void) ...@@ -13655,11 +13845,29 @@ unsigned long psu_mio_init_data(void)
* Master Tri-state Enable for pin 57, active high * Master Tri-state Enable for pin 57, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0
   
* Master Tri-state Enable for pin 58, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0
* Master Tri-state Enable for pin 59, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0
* Master Tri-state Enable for pin 60, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0
* Master Tri-state Enable for pin 61, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0
* Master Tri-state Enable for pin 62, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0
* Master Tri-state Enable for pin 63, active high
* PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0
* MIO pin Tri-state Enables, 63:32 * MIO pin Tri-state Enables, 63:32
* (OFFSET, MASK, VALUE) (0XFF180208, 0x03FFFFFFU ,0x00000000U) * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00000000U)
*/ */
PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET, PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET,
0x03FFFFFFU, 0x00000000U); 0xFFFFFFFFU, 0x00000000U);
/*##################################################################### */ /*##################################################################### */
   
/* /*
......
...@@ -23290,6 +23290,18 @@ ...@@ -23290,6 +23290,18 @@
#define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0 #define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0
#undef IOU_SLCR_MIO_PIN_57_OFFSET #undef IOU_SLCR_MIO_PIN_57_OFFSET
#define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4 #define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4
#undef IOU_SLCR_MIO_PIN_58_OFFSET
#define IOU_SLCR_MIO_PIN_58_OFFSET 0XFF1800E8
#undef IOU_SLCR_MIO_PIN_59_OFFSET
#define IOU_SLCR_MIO_PIN_59_OFFSET 0XFF1800EC
#undef IOU_SLCR_MIO_PIN_60_OFFSET
#define IOU_SLCR_MIO_PIN_60_OFFSET 0XFF1800F0
#undef IOU_SLCR_MIO_PIN_61_OFFSET
#define IOU_SLCR_MIO_PIN_61_OFFSET 0XFF1800F4
#undef IOU_SLCR_MIO_PIN_62_OFFSET
#define IOU_SLCR_MIO_PIN_62_OFFSET 0XFF1800F8
#undef IOU_SLCR_MIO_PIN_63_OFFSET
#define IOU_SLCR_MIO_PIN_63_OFFSET 0XFF1800FC
#undef IOU_SLCR_MIO_PIN_64_OFFSET #undef IOU_SLCR_MIO_PIN_64_OFFSET
#define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100 #define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100
#undef IOU_SLCR_MIO_PIN_65_OFFSET #undef IOU_SLCR_MIO_PIN_65_OFFSET
...@@ -26099,6 +26111,310 @@ ...@@ -26099,6 +26111,310 @@
#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 #define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U #define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U
   
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
* lk- (RX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U
/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp-
* (Asserted to end or interrupt transfers)
*/
#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK
#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2
#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U
/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
*/
#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK
#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3
#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U
/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_
* rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
* , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
* TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl
* k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
* t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
* Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK
#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
* 0]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U
/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data
* bus)
*/
#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK
#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2
#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U
/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
*/
#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK
#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3
#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U
/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy
* _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
* 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
* TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
* utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
* T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
* atabus)
*/
#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK
#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
* 1]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U
/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
* ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data
* bus)
*/
#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK
#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2
#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U
/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
* Used
*/
#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK
#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3
#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U
/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g
* pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy
* _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
* 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
* G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
* Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
* er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK
#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5
#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U
/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
* 2]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL
#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK
#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000
#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1
#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U