4 working channels producing ramp signal

meta-adi/grand_zcu7/project-spec/configs/config

@@ -285,4 +285,8 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
 CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
 CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
 CONFIG_USER_LAYER_2=""
+
+
+
+
 CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"

meta-adi/grand_zcu7/project-spec/configs/config.old

@@ -186,7 +186,7 @@ CONFIG_SUBSYSTEM_MACHINE_NAME="template"
 #
 CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y
 CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y
-CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"
+
 CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""
 # CONFIG_SUBSYSTEM_DTB_OVERLAY is not set
 # CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set
@@ -285,3 +285,4 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r
 CONFIG_USER_LAYER_0="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-core"
 CONFIG_USER_LAYER_1="/home/rene/Data/FPGA_workdir/adi/hdl/meta-adi/meta-adi-xilinx"
 CONFIG_USER_LAYER_2=""
+CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,tcp ip=192.168.10.2:192.168.10.1 rw"

meta-adi/grand_zcu7/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/ad9680_debug.c

@@ -606,7 +606,7 @@ static const struct iio_event_spec ad9680_events[] = {
 	.scan_index = _chan,						\
 	.scan_type = {							\
 		.sign = 'S',						\
-		.realbits = 14,						\
+		.realbits = 16,						\
 		.storagebits = 16,					\
 		.shift = 0,						\
 	},								\
@@ -941,10 +941,19 @@ static int ad9680_setup_link(struct spi_device *spi,
 	val |= ilog2(config->num_converters) << 3;
 	val |= ilog2(config->num_lanes) << 6;
 
+	ret |= ad9680_spi_write(spi, 0x580, config->did);
 	ret |= ad9680_spi_write(spi, 0x581, config->bid);
 
 	ret = ad9680_spi_write(spi, 0x570, val); // Quick config
 
+	for (i = 0; i < config->num_lanes; i++) {
+		ret |= ad9680_spi_write(spi, 0x583 + i, config->lid[i]);
+
+		val = config->lane_mux[i];
+		val |= val << 4;
+		ret |= ad9680_spi_write(spi, 0x5b2 + i + (i / 2), val);
+	}
+
 	val = config->num_lanes - 1;
 	val |= config->scrambling ? 0x80 : 0x00;
 	ret |= ad9680_spi_write(spi, 0x58b, val);
@@ -1029,7 +1038,7 @@ static int ad9680_setup(struct spi_device *spi, bool ad9234)
 		link_config.lane_mux[i] = i;
 	}
 	link_config.num_converters = 2;
-	link_config.octets_per_frame = 2;
+	link_config.octets_per_frame = 1;
 	link_config.frames_per_multiframe = 32;
 	link_config.converter_resolution = ad9234 ? 12 : 14;
 	link_config.bits_per_sample = 16;
@@ -1106,14 +1115,8 @@ static int ad9694_setup_jesd204_link(struct axiadc_converter *conv,
 		sysref_rate = DIV_ROUND_CLOSEST(sample_rate, 128);
 	else
 		sysref_rate = DIV_ROUND_CLOSEST(sample_rate, 32);
-        lane_rate_kHz = DIV_ROUND_CLOSEST(sample_rate, 50);
-		dev_info(&conv->spi->dev, "RH: Lane rate %lu Mbps is",
-			lane_rate_kHz / 1000);
-        dev_info(&conv->spi->dev, "RH: Sysref rate %lu Mbps is",
-		    sysref_rate);
-        dev_info(&conv->spi->dev, "RH: Sample rate %i Mbps is",
-		    sample_rate);            
-            
+	lane_rate_kHz = DIV_ROUND_CLOSEST(sample_rate, 50);
+
 	if (lane_rate_kHz < 1687500 || lane_rate_kHz > 15000000) {
 		dev_err(&conv->spi->dev, "Lane rate %lu Mbps out of bounds. Must be between 1687.5 and 15000 Mbps",
 			lane_rate_kHz / 1000);
@@ -1172,24 +1175,24 @@ static int ad9694_setup(struct spi_device *spi)
 	ad9680_spi_write(spi, 0x000, 0x81); /* RESET */
 	mdelay(5);
 
-	/* Configure A/B and C/D */
+	/* Configure A/B */
 	ret |= ad9680_spi_write(spi, 0x009, 0x03); /* select pair A/B */
 	ret |= ad9680_spi_write(spi, 0x008, 0x03); /* select both channels */
 
 	ret |= ad9680_spi_write(spi, 0x108, 0x00); /* Clock divider = 1 */
 
 	memset(&link_config, sizeof(link_config), 0x00);
+	link_config.did = 0;
 	link_config.bid = 0;
-//	link_config.did = 0;
 	link_config.num_lanes = 2;
-	//for (i = 0; i < link_config.num_lanes; i++) {
-		//link_config.lid[i] = i;
-		//link_config.lane_mux[i] = i;
-	//}
+	for (i = 0; i < link_config.num_lanes; i++) {
+		link_config.lid[i] = i;
+		link_config.lane_mux[i] = i;
+	}
 	link_config.num_converters = 2;
 	link_config.octets_per_frame = 2;
 	link_config.frames_per_multiframe = 32;
-	link_config.converter_resolution = 14;
+	link_config.converter_resolution = 16;
 	link_config.bits_per_sample = 16;
 	link_config.scrambling = true;
 
@@ -1211,67 +1214,6 @@ static int ad9694_setup(struct spi_device *spi)
 	ret |= ad9680_spi_write(spi, 0x001, 0x02); /* datapath soft reset */
 	mdelay(1);
 
-
-	///* Configure A */
-	ret |= ad9680_spi_write(spi, 0x009, 0x01); /* select link A/B (0x01), select link C/D (0x10)  */
-	ret |= ad9680_spi_write(spi, 0x008, 0x01); /* select conv A/C (0x01), select conv B/D (0x10)  */
-
-	link_config.did = 0;
-	link_config.lid[0] = 0;
-    link_config.lane_mux[0] = 0;
-
-    ret = ad9680_spi_write(spi, 0x580, 0x0); /*config->did); */
-    ret |= ad9680_spi_write(spi, 0x583, 0x0); /*config->lid[0]); */
-    ret |= ad9680_spi_write(spi, 0x5b2, 0x0); /*config->lane_mux[0]); */
-	ret |= ad9680_spi_write(spi, 0x001, 0x02); /* datapath soft reset */
-    ret = ad9680_spi_read(conv->spi, 0x58b); /*read lanes per link */
-	mdelay(1);
-    
-    dev_info(&conv->spi->dev, "RH: config ADC A done %i ret is",
-        ret);
-            
- 	///* Configure B */
-	ret |= ad9680_spi_write(spi, 0x009, 0x01); /* select link A/B (0x01), select link C/D (0x10)  */
-	ret |= ad9680_spi_write(spi, 0x008, 0x02); /* select conv A/C (0x01), select conv B/D (0x10)  */
-
-    ret = ad9680_spi_write(spi, 0x580, 0x1); /*config->did); */
-    ret |= ad9680_spi_write(spi, 0x585, 0x1); /*config->lid[0]); */
-    ret |= ad9680_spi_write(spi, 0x5b3, 0x1); /*config->lane_mux[0]); */
-	ret |= ad9680_spi_write(spi, 0x001, 0x02); /* datapath soft reset */
-    ret = ad9680_spi_read(conv->spi, 0x58b); /*read lanes per link */
-	mdelay(1);
-
-    dev_info(&conv->spi->dev, "RH: config ADC B done %i ret is",
-        ret);
-        
-	///* Configure C */
-	ret |= ad9680_spi_write(spi, 0x009, 0x02); /* select link A/B (0x01), select link C/D (0x10)  */
-	ret |= ad9680_spi_write(spi, 0x008, 0x01); /* select conv A/C (0x01), select conv B/D (0x10)  */
-
-    ret = ad9680_spi_write(spi, 0x580, 0x2); /*config->did); */
-    ret |= ad9680_spi_write(spi, 0x583, 0x2); /*config->lid[0]); */
-    ret |= ad9680_spi_write(spi, 0x5b2, 0x2); /*config->lane_mux[0]); */
-	ret |= ad9680_spi_write(spi, 0x001, 0x02); /* datapath soft reset */
-    ret = ad9680_spi_read(conv->spi, 0x58b); /*read lanes per link */    
-	mdelay(1);
-    
-    dev_info(&conv->spi->dev, "RH: config ADC C done %i ret is",
-        ret);
-            
- 	///* Configure D */
-	ret |= ad9680_spi_write(spi, 0x009, 0x02); /* select link A/B (0x01), select link C/D (0x10)  */
-	ret |= ad9680_spi_write(spi, 0x008, 0x02); /* select conv A/C (0x01), select conv B/D (0x10)  */
-
-    ret = ad9680_spi_write(spi, 0x580, 0x3); /*config->did); */
-    ret |= ad9680_spi_write(spi, 0x585, 0x3); /*config->lid[0]); */
-    ret |= ad9680_spi_write(spi, 0x5b3, 0x3); /*config->lane_mux[0]); */
-	ret |= ad9680_spi_write(spi, 0x001, 0x02); /* datapath soft reset */
-    ret = ad9680_spi_read(conv->spi, 0x58b); /*read lanes per link */    
-	mdelay(1);     
-
-    dev_info(&conv->spi->dev, "RH: config ADC D done %i ret is",
-        ret);
-        
 	ret = ad9694_setup_jesd204_link(conv, conv->adc_clk);
 	if (ret < 0)
 		return ret;
@@ -1417,9 +1359,6 @@ static int ad9680_write_raw(struct iio_dev *indio_dev,
 		}
 
 		ret = clk_set_rate(conv->clk, r_clk);
-        dev_info(&conv->spi->dev, "RH: AD9694 sample clk %ul\n",
-			 r_clk);
-             
 		if (ret < 0)
 			return ret;
 		break;

meta-adi/grand_zcu7/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend

+
+#file://0001-only-regs.patch
+#file://0001-sample-rate-500MHz.patch 
+#file://0001-sample-rate-500MHz-v2.patch 
+#file://0001-new-link-params.patch 
+#file://0001-back-to-2-lanes.patch 
+#file://0001-back-to-2-octets.patch 
+#file://0001-removed-1link-function.patch 
+#file://0001-changed-ADC-definition.patch 
+
+#23 Jul
+#file://0001-lane_mux-only.patch 
+#file://0001-reduced-sample-rate-added-quick-config.patch 
+#file://0001-replaced-debug-code.patch 
+
 SRC_URI += "file://user_2020-07-07-12-40-00.cfg \
             file://user_2020-07-09-11-00-00.cfg \
             "
@@ -5,11 +20,10 @@ SRC_URI += "file://user_2020-07-07-12-40-00.cfg \
 SRC_URI_append += " \
 file://0001-debug-ad9680.patch \
 file://0001-debug-txcvr.patch \
-file://0001-changed-lane-parameters.patch \
-file://0001-changed-AD9694_CHAN-def.patch \
-file://0001-conv_res14b.patch \
-file://0001-2conv-2lanes.patch \
+file://0001-disabled-watchdog.patch \
+file://0001-disabled-watchdog-rest.patch \
+file://0001-changed-resolution-and-octets.patch \
+file://0001-sample-rate-and-define.patch \
 "
 
 FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
-

meta-adi/meta-adi-xilinx/recipes-bsp/device-tree/files/zynqmp-zu7cg-rev1-ad9694.dts

@@ -79,8 +79,11 @@
             clock-names = "s_axi_aclk", "device_clk", "lane_clk";
             
             adi,subclass = <0>;
-            adi,octets-per-frame = <1>;
             adi,frames-per-multiframe = <32>;
+            adi,octets-per-frame = <2>;
+            adi,converter-resolution = <16>;
+            adi,bits-per-sample = <16>;
+            adi,converters-per-device = <4>;      
 
             #clock-cells = <0>;
             clock-output-names = "jesd_adc_lane_clk";
@@ -94,7 +97,7 @@
             clock-names = "conv";
             
             adi,sys-clk-select = <3>;
-            adi,out-clk-select = <4>;
+            adi,out-clk-select = <3>;
             adi,use-lpm-enable;
             /* RH: Change to QPLL see zynqMP datasheet max line rate CPLL=8.5Gb/s */
             /* adi,use-cpll-enable; */