change to 500MHz sampling rate

meta-adi/meta-adi-xilinx/recipes-bsp/device-tree/files/zynqmp-zu7cg-rev1-ad9694.dts

@@ -229,7 +229,7 @@
                           <27000000>, /* out 0 */
                           <300000000>,
                           <250000000>, /*250 MHz */
-                          <1000000000>;
+                          <500000000>; /*500 MHz */
 
         out@1 {
             /* PL_DDR_CLK (300MHz) */
@@ -250,7 +250,7 @@
         };
 
         out@3 {
-            /* ADC_REF_CLK (1000MHz) */
+            /* ADC_REF_CLK (500MHz) */
             reg = <3>;
             silabs,format = <1>; /* LVDS 3v3 */
             silabs,common-mode = <3>;