added constraint to pass timing when using ILA

projects/grand/zu7cg/system_constr.xdc

@@ -81,3 +81,6 @@ set_property  -dict {PACKAGE_PIN  K1  } [get_ports rx_data_n[3]]
 #set_property LOC GTHE4_CHANNEL_X1Y9  [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe4_channel}]
 
 #create_clock -name tx_div_clk   -period  3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
+# remove when ila's are removed from firmware
+set_max_delay -from [get_clocks rx_div_clk] -to [get_clocks clk_pl_0] 2.0
+