Commit f706ed2b authored by Rene Habraken's avatar Rene Habraken
Browse files

board files

parent 37ed7193
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<board schema_version="2.1" vendor="xilinx.com" name="zu7cg" display_name="Zynq UltraScale+ ZU7CG GRAND proto_v1" url="www.xilinx.com/zcu102" preset_file="preset.xml">
<images>
<image name="werknemerpas.jpeg" display_name="ZU7CG BOARD" sub_type="board">
<image name="zcu7cg_v1.jpeg" display_name="ZU7CG BOARD" sub_type="board">
<description>ZCU102 Board File Image</description>
</image>
</images>
......@@ -26,7 +26,7 @@
<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
</preferred_ips>
</interface>
<interface mode="slave" name="user_si570_sysclk" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="user_si570_sysclk">
<interface mode="slave" name="user_si5340_sysclk" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="user_si5340_sysclk">
<parameters>
<parameter name="frequency" value="300000000"/>
</parameters>
......@@ -34,14 +34,14 @@
<preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="CLK_P" physical_port="user_si570_sysclk_p" dir="in">
<port_map logical_port="CLK_P" physical_port="user_si5340_sysclk_p" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="user_si570_sysclk_p"/>
<pin_map port_index="0" component_pin="user_si5340_sysclk_p"/>
</pin_maps>
</port_map>
<port_map logical_port="CLK_N" physical_port="user_si570_sysclk_n" dir="in">
<port_map logical_port="CLK_N" physical_port="user_si5340_sysclk_n" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="user_si570_sysclk_n"/>
<pin_map port_index="0" component_pin="user_si5340_sysclk_n"/>
</pin_maps>
</port_map>
</port_maps>
......@@ -99,43 +99,6 @@
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="iic1_pl" type="xilinx.com:interface:iic_rtl:1.0" of_component="iic1_pl">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="SDA_I" physical_port="iic1_main_sda_i" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="IIC1_SDA_MAIN"/>
</pin_maps>
</port_map>
<port_map logical_port="SDA_O" physical_port="iic1_main_sda_o" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="IIC1_SDA_MAIN"/>
</pin_maps>
</port_map>
<port_map logical_port="SDA_T" physical_port="iic1_main_sda_t" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="IIC1_SDA_MAIN"/>
</pin_maps>
</port_map>
<port_map logical_port="SCL_I" physical_port="iic1_main_scl_i" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="IIC1_SCL_MAIN"/>
</pin_maps>
</port_map>
<port_map logical_port="SCL_O" physical_port="iic1_main_scl_o" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="IIC1_SCL_MAIN"/>
</pin_maps>
</port_map>
<port_map logical_port="SCL_T" physical_port="iic1_main_scl_t" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="IIC1_SCL_MAIN"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="ddr4_sdram" type="xilinx.com:interface:ddr4_rtl:1.0" of_component="ddr4_sdram" preset_proc="ddr4_sdram_preset">
<description>DDR4 board interface, it can use DDR4 controller IP for connection. </description>
......@@ -304,18 +267,16 @@
</port_map>
</port_maps>
</interface>
<interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
<interface mode="master" name="push_buttons_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_3bits" preset_proc="push_buttons_3bits_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri" dir="in" left="4" right="0">
<port_map logical_port="TRI_I" physical_port="push_buttons_3bits_tri" dir="in" left="2" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="GPIO_SW_C"/>
<pin_map port_index="1" component_pin="GPIO_SW_W"/>
<pin_map port_index="2" component_pin="GPIO_SW_S"/>
<pin_map port_index="3" component_pin="GPIO_SW_E"/>
<pin_map port_index="4" component_pin="GPIO_SW_N"/>
</pin_maps>
</port_map>
</port_maps>
......@@ -323,8 +284,8 @@
</interfaces>
</component>
<component name="ps8_fixedio" display_name="PS8 fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
<component name="user_si570_sysclk" display_name="User Programmable differential clock" type="chip" sub_type="system_clock" major_group="Clock Sources" part_name="SI5341B" vendor="Silicon Labs" spec_url="www.silabs.com">
<description>SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock</description>
<component name="user_si5340_sysclk" display_name="User Programmable differential clock" type="chip" sub_type="system_clock" major_group="Clock Sources" part_name="SI5340" vendor="Silicon Labs" spec_url="www.silabs.com">
<description>SI5340 based User programmable differential 300 MHz Clock. Can be used for PL DDR4 input system clock</description>
<parameters>
<parameter name="frequency" value="300000000"/>
</parameters>
......@@ -339,9 +300,6 @@
<component name="iic0_pl" display_name="PL IIC0" type="chip" sub_type="mux" major_group="Miscellaneous">
<description>PL I2C0</description>
</component>
<component name="iic1_pl" display_name="PL IIC1" type="chip" sub_type="mux" major_group="Miscellaneous">
<description>PL I2C1</description>
</component>
<component name="ddr4_sdram" display_name="DDR4 SDRAM" type="chip" sub_type="ddr" major_group="External Memory" part_name="MT40A256M16GE-075E" vendor="Micron" spec_url="https://www.micron.com/parts/dram/ddr4-sdram/mt40a256m16ge-075e">
<description>2GB DDR4 SDRAM memory SODIMM</description>
<parameters>
......@@ -360,8 +318,8 @@
<description>LEDs, 7 to 0, Active High</description>
</component>
<component name="push_buttons_5bits" display_name="Push buttons" type="chip" sub_type="push_button" major_group="General Purpose Input or Output" part_name="TL3301EP100QG" vendor="ESwitch">
<description>Push Buttons, C W E S N, Active High</description>
<component name="push_buttons_3bits" display_name="Push buttons" type="chip" sub_type="push_button" major_group="General Purpose Input or Output" part_name="TL3301EP100QG" vendor="ESwitch">
<description>Push Buttons, C W S, Active High</description>
</component>
</components>
<jtag_chains>
......@@ -375,9 +333,6 @@
</connection>
<connection name="part0_iic0_pl" component1="part0" component2="iic0_pl">
<connection_map name="part0_iic0_pl" typical_delay="5" c1_st_index="6" c1_end_index="7" c2_st_index="0" c2_end_index="1"/>
</connection>
<connection name="part0_iic1_pl" component1="part0" component2="iic1_pl">
<connection_map name="part0_iic1_pl" typical_delay="5" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
</connection>
<connection name="part0_ddr_sdram" component1="part0" component2="ddr4_sdram">
<connection_map name="part0_dip_switches_4bits_1" typical_delay="5" c1_st_index="10" c1_end_index="57" c2_st_index="0" c2_end_index="47"/>
......@@ -385,8 +340,8 @@
<connection name="part0_reset" component1="part0" component2="reset">
<connection_map name="part0_reset_1" typical_delay="5" c1_st_index="58" c1_end_index="58" component2="reset" c2_st_index="0" c2_end_index="0"/>
</connection>
<connection name="part0_user_si570_sysclk" component1="part0" component2="user_si570_sysclk">
<connection_map name="part0_user_si570_sysclk_1" typical_delay="5" c1_st_index="0" c1_end_index="1" c2_st_index="59" c2_end_index="60"/>
<connection name="part0_user_si5340_sysclk" component1="part0" component2="user_si5340_sysclk">
<connection_map name="part0_user_si5340_sysclk_1" typical_delay="5" c1_st_index="0" c1_end_index="1" c2_st_index="59" c2_end_index="60"/>
</connection>
<connection name="part0_dip_switches_8bits" component1="part0" component2="dip_switches_8bits">
<connection_map name="part0_dip_switches_8bits_1" typical_delay="5" c1_st_index="61" c1_end_index="68" c2_st_index="0" c2_end_index="7"/>
......@@ -394,8 +349,8 @@
<connection name="part0_led_8bits" component1="part0" component2="led_8bits">
<connection_map name="part0_led_8bits_1" typical_delay="5" c1_st_index="69" c1_end_index="76" c2_st_index="0" c2_end_index="7"/>
</connection>
<connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
<connection_map name="part0_push_buttons_5bits_1" typical_delay="5" c1_st_index="77" c1_end_index="81" c2_st_index="0" c2_end_index="4"/>
<connection name="part0_push_buttons_3bits" component1="part0" component2="push_buttons_3bits">
<connection_map name="part0_push_buttons_3bits_1" typical_delay="5" c1_st_index="77" c1_end_index="81" c2_st_index="0" c2_end_index="4"/>
</connection>
</connections>
......@@ -404,7 +359,7 @@
<ip_associated_rule name="default">
<ip vendor="xilinx.com" library="ip" name="ddr4" version="*" ip_interface="C0_SYS_CLK">
<associated_board_interfaces>
<associated_board_interface name="user_si570_sysclk" order="0"/>
<associated_board_interface name="user_si5340_sysclk" order="0"/>
</associated_board_interfaces>
</ip>
</ip_associated_rule>
......
This diff is collapsed.
This diff is collapsed.
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment