Skip to content
GitLab
Menu
Projects
Groups
Snippets
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
Open sidebar
sovereign
why3-avr
Commits
2ad0ce55
Commit
2ad0ce55
authored
Oct 25, 2017
by
Marc Schoolderman
Browse files
fix
parent
40956600
Changes
1
Show whitespace changes
Inline
Side-by-side
paper.tex
View file @
2ad0ce55
...
...
@@ -237,6 +237,7 @@ val cf: cpu_flag
\end{verbatim}
Reasoning about the carry flag as an integer allows for the specification of the
\texttt
{
ADD
}
instruction as follows:
\newpage
\begin{verbatim}
val add (dst src: register): unit
writes
{
cf, reg
}
...
...
@@ -544,7 +545,7 @@ are modified by the code inside it, and are used to update the \emph{ghost regis
\label
{
fig:abstractblock
}
\end{figure}
In general, if assembly code is hand-written (or generated using a simple process),
such inform
ation is expected to be available for
In general, if assembly code is hand-written (or generated using a simple process),
document
ation is expected to be available for
complicated routines, and should be sufficient to inform a partitioning of it into abstract blocks. If assembly code is
written with verification in mind, it should also be possible to instruct programmers to indicate potential blocks,
or even to employ verification already during the development process.
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment