Commit 5c031638 authored by thomas@cs.ru.nl's avatar thomas@cs.ru.nl

Fixed issues with newlines (changed all CR to LF

parent 65ea2538
cc=A Condition Code (CC) encodes a result of a comparison. Four bits are used to encode the fact that the result of a cmp instruction is zero (Z), negative (N), a carry was needed (C) or overflow was detected (V). conditioncode=@cc sr=SR stands for Status Register. The status, called SR (status register) is not a real register but just an interpretation of the top of the stack. The top of the stack is used to store the condition codes resulting after a compare. Four bits, Z, N, C and V of the SR are used to encode the comparison result being zero, negative, carried and overflowed. These bits are only used by branches on conditions (i.e. beq). statusbits=See SR. prepostcondition=A kind of pre and postcondition is used to denote the effect of instructions. Behaviour is expressed using equations relating the state of the machine before (pre) execution of an instruction to the state after (post). Values of memory (M), registers (PC,SP,MP,RR) are subscripted with 'pre' resp 'post' to refer to the respective values before/after execution. No equation for a value means that the pre and post values are equal.
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cc=A Condition Code (CC) encodes a result of a comparison. Four bits are used to encode the fact that the result of a cmp instruction is zero (Z), negative (N), a carry was needed (C) or overflow was detected (V).
conditioncode=@cc
sr=SR stands for Status Register. The status, called SR (status register) is not a real register but just an interpretation of the top of the stack. The top of the stack is used to store the condition codes resulting after a compare. Four bits, Z, N, C and V of the SR are used to encode the comparison result being zero, negative, carried and overflowed. These bits are only used by branches on conditions (i.e. beq).
statusbits=See SR.
prepostcondition=A kind of pre and postcondition is used to denote the effect of instructions. Behaviour is expressed using equations relating the state of the machine before (pre) execution of an instruction to the state after (post). Values of memory (M), registers (PC,SP,MP,RR) are subscripted with 'pre' resp 'post' to refer to the respective values before/after execution. No equation for a value means that the pre and post values are equal.
cmp_descr=Compare. Replaces 2 top stack values with the status of the comparison of those values. The status is put in SR. See also brf. cmp_prepost=SP_post = SP_pre - 1, M_post[SP_post] = status(M_pre[SP_pre - 1] - M[SP_pre]) cmp_example=ldl -2 ; if x /= 1 then x = 1, ldc 1, cmp, beq skipLabel, ldc 1, stl -2, skipLabel: ... beq_descr=Branch on condition. Notation bcc, where the cc in bcc can be eq (equal), ne (not equal), lt (less than), gt (greater than), le (less or equal) or ge (greater or equal). And some others not used often: pl (plus), mi (minus), cc (carry clear), cs (carry set), hi (high), ls (low or same). beq_prepost=SP_post = SP_pre - 1, PC_post = PC_pre + M_pre[PC_pre + 1] + 2 (if condition matches) beq_example=@cmp_example bne_descr=@beq_descr bne_prepost=@beq_prepost bne_example=@beq_example blt_descr=@beq_descr blt_prepost=@beq_prepost blt_example=@beq_example ble_descr=@beq_descr ble_prepost=@beq_prepost ble_example=@beq_example bgt_descr=@beq_descr bgt_prepost=@beq_prepost bgt_example=@beq_example bge_descr=@beq_descr bge_prepost=@beq_prepost bge_example=@beq_example
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cmp_descr=Compare. Replaces 2 top stack values with the status of the comparison of those values. The status is put in SR. See also brf.
cmp_prepost=SP_post = SP_pre - 1, M_post[SP_post] = status(M_pre[SP_pre - 1] - M[SP_pre])
cmp_example=ldl -2 ; if x /= 1 then x = 1, ldc 1, cmp, beq skipLabel, ldc 1, stl -2, skipLabel: ...
beq_descr=Branch on condition. Notation bcc, where the cc in bcc can be eq (equal), ne (not equal), lt (less than), gt (greater than), le (less or equal) or ge (greater or equal). And some others not used often: pl (plus), mi (minus), cc (carry clear), cs (carry set), hi (high), ls (low or same).
beq_prepost=SP_post = SP_pre - 1, PC_post = PC_pre + M_pre[PC_pre + 1] + 2 (if condition matches)
beq_example=@cmp_example
bne_descr=@beq_descr
bne_prepost=@beq_prepost
bne_example=@beq_example
blt_descr=@beq_descr
blt_prepost=@beq_prepost
blt_example=@beq_example
ble_descr=@beq_descr
ble_prepost=@beq_prepost
ble_example=@beq_example
bgt_descr=@beq_descr
bgt_prepost=@beq_prepost
bgt_example=@beq_example
bge_descr=@beq_descr
bge_prepost=@beq_prepost
bge_example=@beq_example
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# General help info for Simple Stack Machine registers=Eight registers are available, some of which have a specific purpose. A register is private location in a processor, often faster accessible then external memory. Currently the Program Counter (PC), Stack Pointer (SP), Mark Pointer (MP) and Return Register (RR) as well as freely usable scratch registers are available, respectively identified by numbers 0..7. Registers are identified by the name R<x>, where <x> is the register number. Register with a specific purpose are also named with the name indicating their purpose. PC=The Program Counter (PC) is used to remember what the current next instruction is. It contains the address (i.e. points to) the location of the next instruction. The machine fetches an instruction from the location pointed to by the PC. After each fetch it is automatically updated to point to the next instruction. programcounter=@PC SP=The Stack Pointer (SP) is used to push and pop values for usage in expression evaluation. The Stack is also used to store variables. These are often accessed via the MP. stackpointer=@SP MP=The Mark Pointer (MP) is used to access local variables, allocated on the stack. Each variable is accessed using a displacement relative to the MP. markpointer=@MP RR=The Return Register (RR) is used to return a value without placing it on a stack. Strictly seen this is not necessary but a convenience, since values also can be passed via the stack. return register=@RR instruction=An instruction is an encoding of some operation, executed in the machine. A set of instructions stored in memory is called the code. Some instructions have inline operands, that is, after their location in the code an extra operand is stored, a constant, e.g. in "ldc 1". In pre/post conditions this location is indicated by M[PCpre+1] since it can be found on that location. The behavior of an instruction is both informally described as well as using pre/postcondifitions. memory=Memory stores words. A word is an 32 bits integer. Currently only a limited amount of memory words is reserver (2000), this is rather arbitrary, in the future memory size will adapt automatically to the amount needed. stack=Stack is the part of memory used to store values needed for evaluating expressions. The stack is located after the code and grows from lower addresses to higher ones. code=Code is the part of memory used to store instructions. It starts at address 0. help=The Simple Stack Runner executes instructions for a hypothetical (and thus simple) machine. See memory, registers, syntax, instruction as starting points for help. syntax=Syntax of instructions (as loaded from file) is: (label:)? (instr arg*)?. In other words, an (optional) instruction preceded by an (optional) label and followed by an argument if required. Comment may start with ";" or "//" (Java/C++ style) and ends at the end of the line. This characters are interpreted as start of comment. A label may be used as an argument. Example: "l1: beq l1 ; comment". labels=A label is an identifier indicating a position in the code. When loading, the code location of a label is calculated (called resolution). This is done in the user interface of the program and after loading labels are not kept consistent (when adding new instructions for example). False=Value False is encoded by a 0. True=Value True is encoded by a -1 (all 1 bit pattern 0xFFFFFFFF). However, when testing in the context of a BRF instruction takes place, anything else than 0 is considered to be True.
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# General help info for Simple Stack Machine
registers=Eight registers are available, some of which have a specific purpose. A register is private location in a processor, often faster accessible then external memory. Currently the Program Counter (PC), Stack Pointer (SP), Mark Pointer (MP) and Return Register (RR) as well as freely usable scratch registers are available, respectively identified by numbers 0..7. Registers are identified by the name R<x>, where <x> is the register number. Register with a specific purpose are also named with the name indicating their purpose.
PC=The Program Counter (PC) is used to remember what the current next instruction is. It contains the address (i.e. points to) the location of the next instruction. The machine fetches an instruction from the location pointed to by the PC. After each fetch it is automatically updated to point to the next instruction.
programcounter=@PC
SP=The Stack Pointer (SP) is used to push and pop values for usage in expression evaluation. The Stack is also used to store variables. These are often accessed via the MP.
stackpointer=@SP
MP=The Mark Pointer (MP) is used to access local variables, allocated on the stack. Each variable is accessed using a displacement relative to the MP.
markpointer=@MP
RR=The Return Register (RR) is used to return a value without placing it on a stack. Strictly seen this is not necessary but a convenience, since values also can be passed via the stack.
return register=@RR
instruction=An instruction is an encoding of some operation, executed in the machine. A set of instructions stored in memory is called the code. Some instructions have inline operands, that is, after their location in the code an extra operand is stored, a constant, e.g. in "ldc 1". In pre/post conditions this location is indicated by M[PCpre+1] since it can be found on that location. The behavior of an instruction is both informally described as well as using pre/postcondifitions.
memory=Memory stores words. A word is an 32 bits integer. Currently only a limited amount of memory words is reserver (2000), this is rather arbitrary, in the future memory size will adapt automatically to the amount needed.
stack=Stack is the part of memory used to store values needed for evaluating expressions. The stack is located after the code and grows from lower addresses to higher ones.
code=Code is the part of memory used to store instructions. It starts at address 0.
help=The Simple Stack Runner executes instructions for a hypothetical (and thus simple) machine. See memory, registers, syntax, instruction as starting points for help.
syntax=Syntax of instructions (as loaded from file) is: (label:)? (instr arg*)?. In other words, an (optional) instruction preceded by an (optional) label and followed by an argument if required. Comment may start with ";" or "//" (Java/C++ style) and ends at the end of the line. This characters are interpreted as start of comment. A label may be used as an argument. Example: "l1: beq l1 ; comment".
labels=A label is an identifier indicating a position in the code. When loading, the code location of a label is calculated (called resolution). This is done in the user interface of the program and after loading labels are not kept consistent (when adding new instructions for example).
False=Value False is encoded by a 0.
True=Value True is encoded by a -1 (all 1 bit pattern 0xFFFFFFFF). However, when testing in the context of a BRF instruction takes place, anything else than 0 is considered to be True.
This diff is collapsed.
lx: ly: l1: lz: ldc 3 ldc 4 ldc -4 ldc 0x5 ldc -0x6 ldc l3 annote SP -3 0 red "Pushed constants" add mul sub bra l2 l3: bra l1 l2: bra l3 ldc l4: bsr l4
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lx:
ly:
l1:
lz: ldc 3
ldc 4
ldc -4
ldc 0x5
ldc -0x6
ldc l3
annote SP -3 0 red "Pushed constants"
add
mul
sub
bra l2
l3: bra l1
l2: bra l3
ldc
l4: bsr l4
LDC 2 LDC 3 ADD
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LDC 2
LDC 3
ADD
LDC 4 LDC 5 MUL LDC 2 LDC 6 MUL ADD
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LDC 4
LDC 5
MUL
LDC 2
LDC 6
MUL
ADD
; ; Iterative version of faculty ; bra main Fac: link 1 ; fac( int n ) LDC 1 ; int res = 1 ; stl 1 FacTst: ldl -2 ; while ( n > 1 ) LDC 1 gt brf FacEnd ldl -2 ; res = res * n ldl 1 mul stl 1 ldl -2 ; n = n - 1 LDC 1 sub stl -2 bra FacTst FacEnd: ldl 1 ; return( res ) str RR unlink sts -1 ret main: LDC 6 bsr Fac ; fac( 6 ) trap 0 halt
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;
; Iterative version of faculty
;
bra main
Fac: link 1 ; fac( int n )
LDC 1 ; int res = 1 ;
stl 1
FacTst: ldl -2 ; while ( n > 1 )
LDC 1
gt
brf FacEnd
ldl -2 ; res = res * n
ldl 1
mul
stl 1
ldl -2 ; n = n - 1
LDC 1
sub
stl -2
bra FacTst
FacEnd: ldl 1 ; return( res )
str RR
unlink
sts -1
ret
main: LDC 6
bsr Fac ; fac( 6 )
trap 0
halt
bra main Fac: link 0 // fac( int n ) ldl -2 // if ( n <= 1 ) LDC 1 le brt FacTh ldl -2 // else return( n * fac( n-1 ) ) ; ldl -2 LDC 1 sub bsr Fac ldr RR mul bra FacEnd FacTh: LDC 1 // then return( 1 ) FacEnd: str RR unlink sts -1 ret main: LDC 6 annote SP 0 0 green argument bsr Fac // fac( 6 ) halt
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bra main
Fac: link 0 // fac( int n )
ldl -2 // if ( n <= 1 )
LDC 1
le
brt FacTh
ldl -2 // else return( n * fac( n-1 ) ) ;
ldl -2
LDC 1
sub
bsr Fac
ldr RR
mul
bra FacEnd
FacTh: LDC 1 // then return( 1 )
FacEnd: str RR
unlink
sts -1
ret
main: LDC 6
annote SP 0 0 green argument
bsr Fac // fac( 6 )
halt
BRA Main DoPtr: LINK 2 LDC 0x33333333 ; i = ... STL 2 LDLA 2 ; pi = & i STL 1 LDL 1 ; i = *pi LDA 0 STL 2 LDC 0x44444444 LDL 1 ; *pi = ... STA 0 LDC 0x55555555 ; invalid ref, *0x55555555 LDA 0 UNLINK RET Main: BSR DoPtr
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BRA Main
DoPtr: LINK 2
LDC 0x33333333 ; i = ...
STL 2
LDLA 2 ; pi = & i
STL 1
LDL 1 ; i = *pi
LDA 0
STL 2
LDC 0x44444444
LDL 1 ; *pi = ...
STA 0
LDC 0x55555555 ; invalid ref, *0x55555555
LDA 0
UNLINK
RET
Main: BSR DoPtr
BRA main Swap2Ints: LINK 1 LDL -3 LDA 0 STL 1 LDL -2 LDA 0 LDL -3 STA 0 LDL -2 LDL 1 STA 0 UNLINK STS -2 AJS -1 RET main: LINK 2 LDC 4 STL 1 LDC 6 STL 2 LDLA 1 LDLA 2 BSR Swap2Ints UNLINK
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BRA main
Swap2Ints: LINK 1
LDL -3
LDA 0
STL 1
LDL -2
LDA 0
LDL -3
STA 0
LDL -2
LDL 1
STA 0
UNLINK
STS -2
AJS -1
RET
main: LINK 2
LDC 4
STL 1
LDC 6
STL 2
LDLA 1
LDLA 2
BSR Swap2Ints
UNLINK
BRA main f: LINK 2 LDL -3 LDL -2 ADD STL 1 LDL -3 LDL -2 MUL STL 2 LDL 2 LDL 1 SUB STR RR UNLINK STS -2 AJS -1 RET g: LINK 1 LDC 3 LDC 4 LDL -2 BSR f LDR RR MUL STL 1 UNLINK STS -1 RET main: LINK 0 LDC 5 BSR g UNLINK
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BRA main
f: LINK 2
LDL -3
LDL -2
ADD
STL 1
LDL -3
LDL -2
MUL
STL 2
LDL 2
LDL 1
SUB
STR RR
UNLINK
STS -2
AJS -1
RET
g: LINK 1
LDC 3
LDC 4
LDL -2
BSR f
LDR RR
MUL
STL 1
UNLINK
STS -1
RET
main: LINK 0
LDC 5
BSR g
UNLINK
BRA main CpInts: LINK 0 CpBeg: LDL -2 LDC 0 EQ BRT CpEnd LDL -2 LDC 1 SUB STL -2 LDL -4 LDL -2 ADD LDA 0 LDL -3 LDL -2 ADD STA 0 BRA CpBeg CpEnd: UNLINK STS -3 AJS -2 RET main: LINK 12 LDLA 1 LDLA 6 LDC 4 BSR CpInts UNLINK
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BRA main
CpInts: LINK 0
CpBeg: LDL -2
LDC 0
EQ
BRT CpEnd
LDL -2
LDC 1
SUB
STL -2
LDL -4
LDL -2
ADD
LDA 0
LDL -3
LDL -2
ADD
STA 0
BRA CpBeg
CpEnd: UNLINK
STS -3
AJS -2
RET
main: LINK 12
LDLA 1
LDLA 6
LDC 4
BSR CpInts
UNLINK
BRA Main DoIf: LINK 1 LDL -2 LDC 2 MOD LDC 0 ne brt Then LDC 0 STL 1 BRA IfEnd Then: LDC 1 STL 1 IfEnd: UNLINK STS -1 RET Main: LDC 10 BSR DoIf LDC 11 BSR DoIf
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BRA Main
DoIf: LINK 1
LDL -2
LDC 2
MOD
LDC 0
ne
brt Then
LDC 0
STL 1
BRA IfEnd
Then: LDC 1
STL 1
IfEnd: UNLINK
STS -1
RET
Main: LDC 10
BSR DoIf
LDC 11
BSR DoIf
BRA main max3: LINK 0 LDL -3 LDL -2 le brt L1 LDL -3 STL -2 L1: LDL -4 LDL -2 le brt L2 LDL -4 STL -2 L2: LDL -2 STR RR UNLINK STS -3 AJS -2 RET main: LINK 0 LDC 4 LDC 5 MUL LDC 2 LDC 8 LDC 6 BSR max3 LDR RR ADD UNLINK
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BRA main
max3: LINK 0
LDL -3
LDL -2
le
brt L1
LDL -3
STL -2
L1: LDL -4
LDL -2
le
brt L2
LDL -4
STL -2
L2: LDL -2
STR RR
UNLINK
STS -3
AJS -2
RET
main: LINK 0
LDC 4
LDC 5
MUL
LDC 2
LDC 8
LDC 6
BSR max3
LDR RR
ADD
UNLINK
BRA main max3: LINK 0 LDL -3 LDL -2 GT BRF L1 LDL -3 STL -2 L1: LDL -4 LDL -2 GT BRF L2 LDL -4 STL -2 L2: LDL -2 STR RR UNLINK STS -3 AJS -2 RET main: LINK 0 LDC 4 LDC 5 MUL LDC 2 LDC 8 LDC 6 BSR max3 LDR RR ADD UNLINK
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BRA main
max3: LINK 0
LDL -3
LDL -2
GT
BRF L1
LDL -3
STL -2
L1: LDL -4
LDL -2
GT
BRF L2
LDL -4
STL -2
L2: LDL -2
STR RR
UNLINK
STS -3
AJS -2
RET
main: LINK 0
LDC 4
LDC 5
MUL
LDC 2
LDC 8
LDC 6
BSR max3
LDR RR
ADD
UNLINK
ldc 4 ldc 5 ldms -1 2 ldms -2 3 ldc 4 ldma 2 5 mul stml 1 4
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ldc 4
ldc 5
ldms -1 2
ldms -2 3
ldc 4
ldma 2 5
mul
stml 1 4
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<html><head><title>SSM Changes</title><meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"></head> <body bgcolor="#FFFFFF"><h2>Changes in SSM</h2><h3></h3><h3>Version 1.3</h3><ul> <li>20020407. <ul> <li>Added backward stepping (undoing).</li> <li>The instructions in the code pane now also display their arguments, as mnemonic if possible.</li> <li>If code changes during execution a warning is printed.</li> </ul> </li></ul><h3></h3><h3>Version 1.2.3</h3><ul> <li>20020213. Fixed documentation errors.</li></ul><h3>Version 1.2.2</h3><ul> <li>20011210. Fixed some weird splitpane behavior and other GUI stuff. The tests now reflect the the instruction set.</li></ul><h3>Version 1.2.1</h3><ul> <li>20010330. Toolbar had disappeared, it now displays again (untested on WinXX JDK1.3)</li></ul><h3></h3><h3></h3><h3>Version 1.2</h3><ul> <li>20010131. Added blockmove instructions, deleted 'cmp' and related 'brcc' instructions. Changed definition of 'sta' (swapping of parameters on stack) to be consistent with 'stma'. The address is now on top.</li></ul><h3>Version 1.1.3</h3><ul> <li>20000928. Repaired documentation bug for 'jsr'.</li></ul><h3></h3><h3>Version 1.1.2</h3><ul> <li>20000914, Added 'brt' instruction. True is 0xFFFFFFFF (-1).</li></ul><h3>Version 1.1.1</h3><ul> <li>20000912, Fixed documentation errors.</li></ul><h3></h3><h3>Version 1.1</h3><ul> <li>20000911, Added instructions 'eq', 'ne', 'lt', 'le', 'gt', 'ge' and 'brf' for comparing purposes. Added 'ldrr' and 'swprr' for register manipulation.</li></ul><h3></h3><h3>Version 1.0.2</h3><ul> <li> 20000911, Fixed examples in help w.r.t. labels &amp; ':'.</li> <li> 20000911, Tables for instruction description fixed width.</li></ul><h3>Version 1.0.1</h3><ul> <li>20000910, Added Trap instruction.</li> <li>20000909, Changed name of instruction 'ld' to 'lds', 'st' to 'sts'. Added 'ldsa', 'ldaa'. All for better orthogonality of instructionset.</li> <li>20000909, Automatic scroll of codepane to position of PC.</li></ul></body></html>
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<html>
<head>
<title>SSM Changes</title>
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
</head>
<body bgcolor="#FFFFFF">
<h2>Changes in SSM</h2>
<h3></h3>
<h3>Version 1.3</h3>
<ul>
<li>20020407.
<ul>
<li>Added backward stepping (undoing).</li>
<li>The instructions in the code pane now also display their arguments,
as mnemonic if possible.</li>
<li>If code changes during execution a warning is printed.</li>
</ul>
</li>
</ul>
<h3></h3>
<h3>Version 1.2.3</h3>
<ul>
<li>20020213. Fixed documentation errors.</li>
</ul>
<h3>Version 1.2.2</h3>
<ul>
<li>20011210. Fixed some weird splitpane behavior and other GUI stuff. The tests
now reflect the the instruction set.</li>
</ul>
<h3>Version 1.2.1</h3>
<ul>
<li>20010330. Toolbar had disappeared, it now displays again (untested on WinXX
JDK1.3)</li>
</ul>
<h3></h3>
<h3></h3>
<h3>Version 1.2</h3>
<ul>
<li>20010131. Added blockmove instructions, deleted 'cmp' and related 'brcc'
instructions. Changed definition of 'sta' (swapping of parameters on stack)
to be consistent with 'stma'. The address is now on top.</li>
</ul>
<h3>Version 1.1.3</h3>
<ul>
<li>20000928. Repaired documentation bug for 'jsr'.</li>
</ul>
<h3></h3>
<h3>Version 1.1.2</h3>
<ul>
<li>20000914, Added 'brt' instruction. True is 0xFFFFFFFF (-1).</li>
</ul>
<h3>Version 1.1.1</h3>
<ul>
<li>20000912, Fixed documentation errors.</li>
</ul>
<h3></h3>
<h3>Version 1.1</h3>
<ul>
<li>20000911, Added instructions 'eq', 'ne', 'lt', 'le', 'gt', 'ge' and 'brf'
for comparing purposes. Added 'ldrr' and 'swprr' for register manipulation.</li>
</ul>
<h3></h3>
<h3>Version 1.0.2</h3>
<ul>
<li> 20000911, Fixed examples in help w.r.t. labels &amp; ':'.</li>
<li> 20000911, Tables for instruction description fixed width.</li>
</ul>
<h3>Version 1.0.1</h3>
<ul>
<li>20000910, Added Trap instruction.</li>
<li>20000909, Changed name of instruction 'ld' to 'lds', 'st' to 'sts'. Added
'ldsa', 'ldaa'. All for better orthogonality of instructionset.</li>
<li>20000909, Automatic scroll of codepane to position of PC.</li>
</ul>
</body>
</html>
/** * Simple Stack Machine * * Written by Atze Dijkstra, atze@cs.uu.nl, * Copyright Utrecht University. * */ package nl.uu.cs.ssm ; import java.util.Enumeration; abstract class AbstractMemoryCellModel extends Model implements MemoryCellModel{ protected void fireCellChange( MemoryCellModel m, MemoryCellEvent ev ) { for( Enumeration e = getListeners() ; e.hasMoreElements() ; ) { MemoryCellListener l = (MemoryCellListener)e.nextElement() ; l.cellChanged( ev ) ; } } protected void fireCellChange( MemoryCellModel m, int cellIndex, int oldCellValue, Modification mdf ) { fireCellChange( m, new MemoryCellEvent( m, cellIndex, oldCellValue, mdf ) ) ; } protected void fireCellChange( MemoryCellModel m, int cellIndex, MemoryAnnotation oldCellValue, Modification mdf ) { fireCellChange( m, new MemoryCellEvent( m, cellIndex, oldCellValue, mdf ) ) ; } public void addMemoryCellListener( MemoryCellListener l ) { addListener( l ) ; } public void removeMemoryCellListener( MemoryCellListener l ) { removeListener( l ) ; } }
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/**
* Simple Stack Machine
*
* Written by Atze Dijkstra, atze@cs.uu.nl,
* Copyright Utrecht University.
*
*/
package nl.uu.cs.ssm ;
import java.util.Enumeration;
abstract class AbstractMemoryCellModel extends Model
implements MemoryCellModel
{
protected void fireCellChange( MemoryCellModel m, MemoryCellEvent ev )
{
for( Enumeration e = getListeners() ; e.hasMoreElements() ; )
{
MemoryCellListener l = (MemoryCellListener)e.nextElement() ;
l.cellChanged( ev ) ;
}
}
protected void fireCellChange( MemoryCellModel m, int cellIndex, int oldCellValue, Modification mdf )
{
fireCellChange( m, new MemoryCellEvent( m, cellIndex, oldCellValue, mdf ) ) ;
}
protected void fireCellChange( MemoryCellModel m, int cellIndex, MemoryAnnotation oldCellValue, Modification mdf )
{
fireCellChange( m, new MemoryCellEvent( m, cellIndex, oldCellValue, mdf ) ) ;
}
public void addMemoryCellListener( MemoryCellListener l )
{
addListener( l ) ;
}
public void removeMemoryCellListener( MemoryCellListener l )
{
removeListener( l ) ;
}
}
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/** * Simple Stack Machine * * Written by Atze Dijkstra, atze@cs.uu.nl, * Copyright Utrecht University. * */ package nl.uu.cs.ssm ; import java.awt.Color; public class ColoredText{ public static final ColoredText blankDefault = new ColoredText( "", Color.gray ) ; private String text ; private Color color ; public ColoredText( String t, Color c ) { text = t ; color = c ; } public String getText() { return text ; } public Color getColor() { return color ; } public String toString() { return "ColoredText " + text ; } }
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/**
* Simple Stack Machine
*
* Written by Atze Dijkstra, atze@cs.uu.nl,
* Copyright Utrecht University.
*
*/
package nl.uu.cs.ssm ;
import java.awt.Color;
public class ColoredText
{
public static final ColoredText blankDefault = new ColoredText( "", Color.gray ) ;
private String text ;
private Color color ;
public ColoredText( String t, Color c )
{
text = t ;
color = c ;
}
public String getText()
{
return text ;
}
public Color getColor()
{
return color ;
}
public String toString()
{
return "ColoredText " + text ;
}
}
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/** * Simple Stack Machine * * Written by Atze Dijkstra, atze@cs.uu.nl, * Copyright Utrecht University. * */ /** * Configuration * */package nl.uu.cs.ssm ; import java.awt.event.KeyEvent; public class Config{ public static final int[] keysLoad = { KeyEvent.VK_O } ; public static final int[] keysReload = { KeyEvent.VK_R } ; public static final int[] keysPause = { KeyEvent.VK_SPACE } ; public static final int[] keysFullForward = { KeyEvent.VK_DOWN } ; public static final int[] keysFullBackward = { KeyEvent.VK_UP } ; public static final int[] keysStep1Forward = { KeyEvent.VK_RIGHT, KeyEvent.VK_SPACE } ; public static final int[] keysStep1Backward = { KeyEvent.VK_LEFT, KeyEvent.VK_BACK_SPACE } ; public static final String extensionSSM = "ssm" ; public static final int allowedAutomaticMemoryIncrease = 100 ; public static final String version() { return "1.3.3" ; } public static final String versionDate() { return "2002 04 15" ; } public static final String author() { return "Atze Dijkstra, Utrecht University" ; } public static final String authorEmail() { return "atze@cs.uu.nl" ; } }
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/**
* Simple Stack Machine
*
* Written by Atze Dijkstra, atze@cs.uu.nl,
* Copyright Utrecht University.
*
*/
/**
* Configuration
*
*/
package nl.uu.cs.ssm ;
import java.awt.event.KeyEvent;
public class Config
{
public static final int[] keysLoad = { KeyEvent.VK_O } ;
public static final int[] keysReload = { KeyEvent.VK_R } ;
public static final int[] keysPause = { KeyEvent.VK_SPACE } ;
public static final int[] keysFullForward = { KeyEvent.VK_DOWN } ;
public static final int[] keysFullBackward = { KeyEvent.VK_UP } ;
public static final int[] keysStep1Forward = { KeyEvent.VK_RIGHT, KeyEvent.VK_SPACE } ;
public static final int[] keysStep1Backward = { KeyEvent.VK_LEFT, KeyEvent.VK_BACK_SPACE } ;
public static final String extensionSSM = "ssm" ;
public static final int allowedAutomaticMemoryIncrease
= 100 ;
public static final String version() { return "1.3.3" ; }
public static final String versionDate() { return "2002 04 15" ; }
public static final String author() { return "Atze Dijkstra, Utrecht University" ; }
public static final String authorEmail() { return "atze@cs.uu.nl" ; }
}
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/** * Simple Stack Machine * * Written by Atze Dijkstra, atze@cs.uu.nl, * Copyright Utrecht University. * */ package nl.uu.cs.ssm ; import java.util.Enumeration; public interface HelpSupplier{ public Enumeration<String> getTopics() ; public String getHelpSupplierName() ; public String getShortSummaryForTopic( String topic ) ; public void getHelpForTopic( String topic, HelpAccumulator acc ) ; }
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/**
* Simple Stack Machine
*
* Written by Atze Dijkstra, atze@cs.uu.nl,
* Copyright Utrecht University.
*
*/
package nl.uu.cs.ssm ;
import java.util.Enumeration;
public interface HelpSupplier
{
public Enumeration<String> getTopics() ;
public String getHelpSupplierName() ;
public String getShortSummaryForTopic( String topic ) ;
public void getHelpForTopic( String topic, HelpAccumulator acc ) ;
}